Exactly my thought. Those are the first chips on 7nm, so first comparison on process advances. Now, there are tweaks between gens, so it would be good to try to tease out the difference on those as best as possible, but is nice. Around December, I expect AMD to show off Epyc 2 publicly, as that is Intel’s release of Cascade-SP/X. That should be the best comparison. Then Qualcomm Snapdragon (which will compare against 10nm prior version of snapdragon IIRC, which is supposed to be similar in density to the Intel 14nm, so it would see amount of performance beyond what an Intel equivalent node offers). Then, finally, released silicon.
Now, AMD did say consumer chips come after the server chips. So the question is whether AMD is doing full volume when releasing EPYC 2 sometime early in 2019, or if AMD will do a paper launch with low supply, then mainstream, then volume around computex, or what their exact roadmap is on that.
Technical reasons aside at the end of the day i see it coming down to economy of scale to get the funds to spend on fabs.
Intel aren’t making as many devices as TSMC and Samsung.
The CPU market has been stagnant for years.
Unless they farm out fab capacity (which will negate their exclusive superior-fab advantage and mean they need to compete purely on design merit) they will be killed by economy of scale.
According to the latest leaks Rome might be eight 7nm processing chips and one 14nm IO chip.
4 posts were merged into an existing topic: Power Architecture in enterprise datacenters
While researching for a post on the thread that was just split off, I came across an article that had this comment from its author, specifically answering my question about IBM’s plans for POWER10:
IBM itself confirmed to me that it was looking at foundries other than GF for Power10, and the only three options are Intel (well, its 10 nanometer) and we all had a laugh about that, or TSMC or Samsung. It will be Samsung. Power9 and Power9′ will be on 14 nanometer or 12 nanometer.
I added the emphasis there. It does make sense though; since everyone always mentions the huge cache sizes on POWER chips, maybe they picked Samsung over TSMC for their experience with memory chips?
I actually think it is due to the IBM/Samsung/GF research joint venture and Samsung having their own GAA being worked on (more applicable beyond the next chips) that may have played a roll in it. But that is my speculation.
Saw a rumor Nvidia may move production to Samsung for the next node as well. I’ve only seen it one place, so well in rumor territory, but something to keep an eye on.
Density of this chip should be about 82,9 MTr/mm²
That is a bit lower than the theoretical density provided at wikichip or semiwiki (forgot which one). Do you have information on what basis that density was calculated on?
Just the amount of transistors(6.9B) and the measured die size(83.3mm²)
They directly compared the CPU and GPU cores of the A11 and A12, and they had shrunk 23 and 37% respectively.
Missed the transistor count (searched for the article in anandtech).
Here is that article, just as a reference:
And I mean no offense, of course, just like to have information and bases for my own understanding. Found the 6.9B in a different article (I’m still on my first cup of coffee this morning, so I apologize if I come off as crass or with tone in my writing, I mean no offense).
Part of the explanation comes from the theoretical max being calculated on the basis of SRAM density, which does not always translate when applied to an actual architecture for numerous reasons. For some reason, though, I wasn’t expecting a 14% lower than theoretical max on density (which may be my own naivete for not comparing prior SRAM densities to final silicon densities to see the average amount off theoretical max from SRAM cells in preparation for this discussion). I also know that AMD has their own custom libraries that will have/cause lower scaling than the theoretical max for a given node (I think they estimated a 2X scaling at 7nm instead of the higher quoted scaling densities from the fabs, if I recall correctly).
None taken, I should have linked the article.
Looking forward to see the anandtech review of the new iphone, their new testing methods are great for seeing real life performance and power efficiency gains.
Intel struggling with capacity on 14nm, and have to invest more in it, this is probably gonna hurt them in the long run.
In a bid to increase production of its 14-nm chips the company is investing an additional $1 billion in its manufacturing sites in Oregon, Arizona, Ireland and Israel that product chips using the said technology. Intel originally planned to spend $14 billion in CapEx this year, but then allocated another billion to boost production capacity of its 14 nm fabs. Intel naturally does not detail how it plans to upgrade the facilities, but $1 billion can buy you many step-and-scan systems to process wafers.
What low power dual core risc chips exist in the magical land of SOC’s that would run as a good HTPC environmet?
Would rockchip be a good solution? The idea is hardware based 264 and 265 solutions.
Intel is splitting its manufacturing group in three.
Technology Development, to be led by CTO Mike Mayberry
Manufacturing and Operations, led by Ann Kelleher
Supply Chain, led by Randhir Thakur
Samsung started their 7nm production with EUVL for select layers.
Intel just dropped to 3rd and last place in the foundry race by the looks of it.