[Solved] Is it possible to use iGPU/APU as primary GPU? (with dGPU installed)

[DS_DV]

Hi,

i got lucky and got a 7900xtx.
Sadly linux does not easily work with video out on a second gpu

Therefor i have to bite the bullet and buy the upgrade to AM5 in hope that the APU from the new 7900 CPUs will be recognized as primary gpu.

Is anyone here who has experience runnign vfio with iGPU/APU and 1 GPU ?
(where iGPU/APU is the host)?

with kind regards

//EDIT1:

It works
I use the X670 Aorus Master (due to it having 3 Display outs over the B650 version)
I opted for Gigabyte since i read that there Primary GPU switch works.
And at least on BIOS version F8 (latest as time of writing) i can chose which GPU is the primary. (i also Forced the internal GPU of the CPU inside AMD CBS settings just for good measure).

[tjw]

yes, it has worked with intel igpu for years, as for AM5 i’m not sure but it should work. it’s a case of going into the uefi, enabling the igpu always, and setting the goard to always init IGPU first, should work fine

[quilt]

On my asus proart x670e it works. In the bios set iGPU as primary and bind dGPU to vfio on boot. No issues. Just check that the board has the relevant options in the bios. Otherwise I think it would still be possible to passthrough but more of a hassle.

[DS_DV]

that sounds great. thanks for the feedback
i explicitly chose the x670 aorus master because of the pcie layout and because in the manual there is a bios option for primary gpu listed.

on x670 there sadly only is auto force apu or force dgpu.
on x570 there where option to choose the pcie device

ofc it would have been much better to get the old setup running
to be precise it would have been ~1400 times better xD

[Janos]

Ryzen 7950X / X670E Taichi VFIO Success (With Notes)

Hello All, Just writing up my findings of moving my QEMU / Libvirt virtual machine with GPU and NVME pass-through from my X570 setup to a new X670E setup. Firstly here are some limitations i have found with the new platform : The initial set of BIOS’ seem to lack a selector for the primary GPU selection mode, this means you cannot force the i…

[DS_DV]

thanks so much for your relpy <3
i now already have my x670 aorus master and a temporary 7700
But it still helps alot!

my iommu groups look ok so far but ill post my output when my 7900xtx replacement arrives

[Janos]

maybe you can help me too, can you please check if the CPU cache size in your Windows VM is correct with your 7700?
The reason why I ask is, I recently helped someone with an 5700G System and have noticed that his Windows VM shows 128MB L3 cache, correct is 16MB.

The easiest way to do this is to use Coreinfo

Coreinfo - Sysinternals

Here an example

C:\Users\user>C:\Users\user\Documents\Coreinfo\Coreinfo64.exe

Coreinfo v3.52 - Dump information on system CPU and memory topology
Copyright (C) 2008-2021 Mark Russinovich
Sysinternals - www.sysinternals.com


AMD EPYC Processor
AMD64 Family 23 Model 1 Stepping 2, AuthenticAMD
Microcode signature: 00000000
HTT             *       Multicore

Administrator rights are required to query information.
Querying CET support requires admin rights
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              -       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          *       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           *       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       -       Supports AVX-512 Foundation instructions
AVX-512-DQ      -       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   -       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      -       Supports AVX-512 conflict detection instructions
AVX-512-BW      -       Supports AVX-512 byte and word instructions
AVX-512-VL      -       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         -       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           -       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   -       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended).
Maximum implemented address width: 48 bits (virtual), 40 bits (physical).

Processor signature: 00800F12

Logical to Physical Processor Map:
**--------------  Physical Processor 0 (Hyperthreaded)
--**------------  Physical Processor 1 (Hyperthreaded)
----**----------  Physical Processor 2 (Hyperthreaded)
------**--------  Physical Processor 3 (Hyperthreaded)
--------**------  Physical Processor 4 (Hyperthreaded)
----------**----  Physical Processor 5 (Hyperthreaded)
------------**--  Physical Processor 6 (Hyperthreaded)
--------------**  Physical Processor 7 (Hyperthreaded)

Logical Processor to Socket Map:
****************  Socket 0

Logical Processor to NUMA Node Map:
********--------  NUMA Node 0
--------********  NUMA Node 1

Approximate Cross-NUMA Node Access Cost (relative to fastest):
     00  01
00: 1.0 1.7
01: 1.5 1.1

Logical Processor to Cache Map:
**--------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
**--------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
****------------  Unified Cache       1, Level 3,    8 MB, Assoc  16, LineSize  64
--**------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
--**------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
----**----------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
----**----------  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
----****--------  Unified Cache       4, Level 3,    8 MB, Assoc  16, LineSize  64
------**--------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
------**--------  Unified Cache       5, Level 2,  512 KB, Assoc   8, LineSize  64
--------**------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
--------**------  Unified Cache       6, Level 2,  512 KB, Assoc   8, LineSize  64
--------****----  Unified Cache       7, Level 3,    8 MB, Assoc  16, LineSize  64
----------**----  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
----------**----  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
------------**--  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--  Instruction Cache   6, Level 1,   64 KB, Assoc   4, LineSize  64
------------**--  Unified Cache       9, Level 2,  512 KB, Assoc   8, LineSize  64
------------****  Unified Cache      10, Level 3,    8 MB, Assoc  16, LineSize  64
--------------**  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**  Instruction Cache   7, Level 1,   64 KB, Assoc   4, LineSize  64
--------------**  Unified Cache      11, Level 2,  512 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
****************  Group 0

C:\Users\user>

[DS_DV]

will do (:
at the moment i am restoring my linux installation (:
As soon as i have the vfiovm running ill make you a print out

[DS_DV]

Sorry for the delay.
sadly i had to return my 7900XTX and than notice that even with the now good replacement the resetbug is worse than with the 6800XT. So refund and get a 4 8 …

so far i still only have the placeholder 7700 in place with the following config:

  <vcpu placement="static">12</vcpu>
  <iothreads>1</iothreads>
  <cputune>
    <vcpupin vcpu="0" cpuset="1,9"/>
    <vcpupin vcpu="1" cpuset="2,10"/>
    <vcpupin vcpu="2" cpuset="3,11"/>
    <vcpupin vcpu="3" cpuset="5,13"/>
    <vcpupin vcpu="4" cpuset="6,14"/>
    <vcpupin vcpu="5" cpuset="7,15"/>
    <emulatorpin cpuset="4,12"/>
    <iothreadpin iothread="1" cpuset="4,12"/>
  </cputune>

that leads to the Coreinfo result:

Coreinfo v3.6 - Dump information on system CPU and memory topology
Copyright (C) 2008-2022 Mark Russinovich
Sysinternals - www.sysinternals.com


AMD Ryzen 7 7700 8-Core Processor
AMD64 Family 25 Model 97 Stepping 2, AuthenticAMD
Microcode signature: 00000000
HTT             *       Multicore
CET             -       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        -       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             *       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              -       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          *       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           *       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       *       Supports AVX-512 Foundation instructions
AVX-512-DQ      *       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   *       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      *       Supports AVX-512 conflict detection instructions
AVX-512-BW      *       Supports AVX-512 byte and word instructions
AVX-512-VL      *       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         -       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   -       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 00000010 (Basic), 80000021 (Extended).
Maximum implemented address width: 48 bits (virtual), 48 bits (physical).

Processor signature: 00A60F12

Logical to Physical Processor Map:
**----------  Physical Processor 0 (Hyperthreaded)
--**--------  Physical Processor 1 (Hyperthreaded)
----**------  Physical Processor 2 (Hyperthreaded)
------**----  Physical Processor 3 (Hyperthreaded)
--------**--  Physical Processor 4 (Hyperthreaded)
----------**  Physical Processor 5 (Hyperthreaded)

Logical Processor to Socket Map:
************  Socket 0

Logical Processor to NUMA Node Map:
************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**----------  Data Cache          0, Level 1,   64 KB, Assoc   2, LineSize  64
**----------  Instruction Cache   0, Level 1,   64 KB, Assoc   2, LineSize  64
**----------  Unified Cache       0, Level 2,  512 KB, Assoc  16, LineSize  64
************  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
--**--------  Data Cache          1, Level 1,   64 KB, Assoc   2, LineSize  64
--**--------  Instruction Cache   1, Level 1,   64 KB, Assoc   2, LineSize  64
--**--------  Unified Cache       2, Level 2,  512 KB, Assoc  16, LineSize  64
----**------  Data Cache          2, Level 1,   64 KB, Assoc   2, LineSize  64
----**------  Instruction Cache   2, Level 1,   64 KB, Assoc   2, LineSize  64
----**------  Unified Cache       3, Level 2,  512 KB, Assoc  16, LineSize  64
------**----  Data Cache          3, Level 1,   64 KB, Assoc   2, LineSize  64
------**----  Instruction Cache   3, Level 1,   64 KB, Assoc   2, LineSize  64
------**----  Unified Cache       4, Level 2,  512 KB, Assoc  16, LineSize  64
--------**--  Data Cache          4, Level 1,   64 KB, Assoc   2, LineSize  64
--------**--  Instruction Cache   4, Level 1,   64 KB, Assoc   2, LineSize  64
--------**--  Unified Cache       5, Level 2,  512 KB, Assoc  16, LineSize  64
----------**  Data Cache          5, Level 1,   64 KB, Assoc   2, LineSize  64
----------**  Instruction Cache   5, Level 1,   64 KB, Assoc   2, LineSize  64
----------**  Unified Cache       6, Level 2,  512 KB, Assoc  16, LineSize  64

Logical Processor to Group Map:
************  Group 0

i hope this helps. When i get the 79*0X3D i can update the Thread

with kind regards

[Janos]

have you set “Host passthrough” for your CPU?

What are your results with latencymon?

Your CPU has 32MB 3Level cache and 1MB (8MB) 2Level cache, for best results your VM should see the correct cache sizes.

try something like this and use hostpasstrough for CPU if not already.
Use “lstopo” to check you CPU topology.

  <memoryBacking>
    <hugepages/>
  </memoryBacking>
  <vcpu placement='static' current='16'>24</vcpu>
  <vcpus>
    <vcpu id='0' enabled='yes' hotpluggable='no'/>
    <vcpu id='1' enabled='yes' hotpluggable='yes'/>
    <vcpu id='2' enabled='yes' hotpluggable='yes'/>
    <vcpu id='3' enabled='yes' hotpluggable='yes'/>
    <vcpu id='4' enabled='no' hotpluggable='yes'/>
    <vcpu id='5' enabled='no' hotpluggable='yes'/>
    <vcpu id='6' enabled='yes' hotpluggable='yes'/>
    <vcpu id='7' enabled='yes' hotpluggable='yes'/>
    <vcpu id='8' enabled='yes' hotpluggable='yes'/>
    <vcpu id='9' enabled='yes' hotpluggable='yes'/>
    <vcpu id='10' enabled='no' hotpluggable='yes'/>
    <vcpu id='11' enabled='no' hotpluggable='yes'/>
    <vcpu id='12' enabled='yes' hotpluggable='yes'/>
    <vcpu id='13' enabled='yes' hotpluggable='yes'/>
    <vcpu id='14' enabled='yes' hotpluggable='yes'/>
    <vcpu id='15' enabled='yes' hotpluggable='yes'/>
    <vcpu id='16' enabled='no' hotpluggable='yes'/>
    <vcpu id='17' enabled='no' hotpluggable='yes'/>
    <vcpu id='18' enabled='yes' hotpluggable='yes'/>
    <vcpu id='19' enabled='yes' hotpluggable='yes'/>
    <vcpu id='20' enabled='yes' hotpluggable='yes'/>
    <vcpu id='21' enabled='yes' hotpluggable='yes'/>
    <vcpu id='22' enabled='no' hotpluggable='yes'/>
    <vcpu id='23' enabled='no' hotpluggable='yes'/>
  </vcpus>
  <iothreads>1</iothreads>
  <cputune>
    <vcpupin vcpu='0' cpuset='1'/>
    <vcpupin vcpu='1' cpuset='13'/>
    <vcpupin vcpu='2' cpuset='2'/>
    <vcpupin vcpu='3' cpuset='14'/>
    <vcpupin vcpu='4' cpuset='3'/>
    <vcpupin vcpu='5' cpuset='15'/>
    <vcpupin vcpu='6' cpuset='4'/>
    <vcpupin vcpu='7' cpuset='16'/>
    <vcpupin vcpu='8' cpuset='7'/>
    <vcpupin vcpu='9' cpuset='19'/>
    <vcpupin vcpu='10' cpuset='8'/>
    <vcpupin vcpu='11' cpuset='20'/>
    <vcpupin vcpu='12' cpuset='9'/>
    <vcpupin vcpu='13' cpuset='21'/>
    <vcpupin vcpu='14' cpuset='10'/>
    <vcpupin vcpu='15' cpuset='22'/>
    <emulatorpin cpuset='5,11,17,23'/>
    <iothreadpin iothread='1' cpuset='0,6,12,18'/>
  </cputune>

for example set here your complete and correct topology and adjust what your VM sees with “vcpu placement”, “vcpus” and cputune

 <cpu mode='host-passthrough' check='none'>
    <topology sockets='1' dies='1' cores='8' threads='2'/>
    <feature policy='require' name='topoext'/>
    <feature policy='disable' name='amd-stibp'/>
  </cpu>

performance_tuning_guide-memory-configuring-huge-pages

[DS_DV]

since i somehow my am5 memory takes more ram my 8gb hugepages + 16gb ram on my 32gb host memory do not work out anymore
Without the vm running i am at 19 to 20 gb used memory

So ill attemt the “finetuning” when my X3D cpu arrives

also i like the idea of dynamic hugepages mentioned in arch wikihttps://wiki.archlinux.org/title/PCI_passthrough_via_OVMF#Dynamic_huge_pages

[Janos]

@DS_DV

dynamic hugepages

haven’t checked yet, will try it with my new system

[softwaretools]

Could you share your IOMMU groupings of the X670 Aorus Master when you have a chance? How is the primary GPU switch working out? And does the board have any option for ACS mode in the BIOS like the Taichi by chance?

Trying to figure out a setup for doing the same as you.

[DS_DV]

Gigabyte X670e Aorus Master IOMMU Groups

So here are my IOMMU Groups with BIOS Version F8 Group 0: [1022:14da] 00:01.0 Host bridge Device 14da Group 1: [1022:14da] 00:02.0 Host bridge Device 14da Group 2: [1022:14db] [R] 00:02.1 PCI bridge Device 14db Group 3: [1022:14db] [R] 00:02.2 PCI b…

[softwaretools]

Thanks!

[lI_Simo_Hayha_Il]

@DS_DV have you manage to setup your system using iGPU as primary? I am having serious trouble with that, and been trying over a week with no success.

I have GB Aorus Master F10a with a 7950X3D and a 6900XT and no matter what I do, I cannot boot from iGPU, Manjaro, always loads on my 6900XT.

Can you please share your BIOS settings and/or GRUB Kernel parameters?

Edit: Can you reply on my post, so I don’t hijack yours?

[Exard3k]

@lI_Simo_Hayha_Il

Can you please share your BIOS settings and/or GRUB Kernel parameters?

I have an AsRock board and the board shipped with no options regarding those settings in the BIOS.
With recent BIOS updates, there are now extensive options regarding primary GPU and submenu dealing with things like enabling/disabling iGPU. Pretty much everything I ever need for my use.

AM5 BIOS options certainly had the early adopter tax built-in. I’m glad this changed as the platform has matured over the last months.

[lI_Simo_Hayha_Il]

@Exard3k

I have an AsRock board and the board shipped with no options regarding those settings in the BIOS.

Mine has these options, and more than needed, but they don’t seem to work, or I am missing something here.

[DS_DV]

some options like primary GPU are sadly not standard.

On AM5 even ASUS only got them in late UEFI Versions and than they never really worked.
That is one of the main reasons i went back to Gigabyte because i knew that they have implemented that functionality and it is working.

I can also confirm that i was working on the Gigabyte X670E Aorus Master with F8 and F10a UEFI versions.

Of course the UEFI Settings do not overwrite the OS.

Fun fact the reason i switched from Gigabyte to ASUS on AM4 (AM2 and AM§ where both Gigabyte) was because on the first UEFi Version on the X370 Boards from Gigabyte you could not even disable onboard devices like Audio / Lan etc.

So compared to the AM4 launch AM5 is pretty polished (except the EXPO/XPM Profile problems)