Welp it’s gonna be a close one - nothing left to do now but to write the first stage bootloader and clench as the two boards are fabbed. Moved some things around so that this whole assembly can still be useful after Devember is done.
Software development time while we wait. I’ll need to write:
First Stage Bootloader (“1SBL”) - embedded in ROM, only function is to poll all bus devices if they are 1) present, 2) alive, and 3) contain a valid second stage bootloader image, and then copy that image into memory before rebooting from the 1SBL ROM region into the primary system memory region.
Second Stage Bootloader (“2SBL”) - contained in an onboard I2C flash IC, comparable to the BIOS on an x86 system. Finds, loads, and executes the OS kernel. In this case, the 2SBL is just going to be a small chunk of diagnostic code that will respond over a serial port that the CPU is alive and the 2SBL was successfully executed, which is the arbitrary point at which I’m calling success.
There are no FPGAs in existence right now. This whole thing was originally going to be on a Lattice MachXO2 (they’re super easy to use), but there are none available and lead times are pushed out until the middle of next year at the earliest.
Development board prices are jacked to the tits. After seeing the Lattice FPGA situation, I was going to grab a Digilent Spartan6 CMOD (FPGA on a little DIP-48 breakout board) - the MSRP used to be $35; they now retail for $90. So, I’ve rejected all of the above and just rolled my own since I have a few old Cyclone III FPGAs on hand.
The LDO regulator inventory has gone to hell. Unless you can make do with a '1117 or are willing to pay $10+ for a single Analog Devices IC, good luck.
Why are all of the 0.1" pin headers gone?! Yeah you can still find what you’re looking for from some random manufacturer if you look hard enough, but it’s nice to have same product line (eg TE BergStik/Wurth WR-PHD/etc) and not just slap whatever you can find on there.
Solid polymer electrolytic caps still exist but are anywhere from 100-350% marked up now.
Just a serial port, two EEPROMs, a couple buttons, and some memory hanging off of an FPGA. Unfortunately, my brilliant ass missed a couple of odd resistor values in the BOM that were for the 1.2V and 2.5V rails’ feedback, so that’s where the demo hardware is gonna wrap for now. Trying to power it up without those rails would just blow the FPGA up.
I’mma finally get around to uploading the firmware, schematics, block diagrams, and the bootloader over the weekend here. And, even if it’s not for Devember I’ll still be working on this and will post updates as I have them.
Wow! Amazing work. I’ve not been following your project as much as I wanted because I have been working on my Masters dissertation and starting a new company. So I just checked in and OMG! I am seriously impressed at the amount of work you have done. Mind blown.
I’ve been updating block diagrams as I go through and clean up the RTL/check it into the SVN repo. I’ll post them here as I get them fixed up. You’ll have to open image in new tab because they’re huge.
Yeah this one will never have a Finished tag in the same way that the X86 architecture doesn’t have a Finished tag, but I’m going to keep chronicling the whole thing for next December when I should hopefully be ready to build a compiler for the thing.
And in somewhat related news, the HDL is being re-targeted to an older FPGA from the mid 90s (Xilinx XC3000A series) which I have several dozen of. Not a major overhaul but some things will need split up. I’ll probably just tear all the functional units out of the core and slap them on a 16(writeback)+16(instruction)-bit bus.
Reason being, due to component shortages I’m completely unable to source any more of the configuration devices for the Altera Cyclone III.
Yep, just the little SOIC-8 flash memory, that they vendor-locked to Intel branded EPCSxx chips. It’ll take a few of them to fit the entire design but I’m actually surprised how easy these are to work with.
Welcome back, Windows 95. The last supported OS for Xilinx Foundation 1.5i (the last IDE for the XC3000 series), and the only one I’ve been able to get it running on.
Currently emulated on an 86Box Pentium II system, but it’s miserable and so I’ve got a good old Intel 486 Overdrive that’s about to become the new HDL development platform.
TL;DR: New FPGAs are expensive and currently nonexistent, so I’m going back to 1995.
Yeah it’s admittedly gonna be more of a trainwreck than I intended for the next couple months, but I intend on sorting everything into a new, more organized thread once I’ve got the design settled into a platform I can actually do some sustainable development on. Until then, I’d just consider this thread more of a brainstorming dump as interesting things come up. Not the sort of thing that’s a great fit for Devember but I figured someone might find it entertaining haha
Check for the DIAG_BOOT flag, taken from an onboard jumper. If set, immediately jump to the DIAG_BOOT subroutine (not implemented yet) where the 2SBL/‘BIOS’ I2C interface can be controlled directly by the root serial port, allowing for that EEPROM to be written/read over serial.
If not, start reading from the 2SBL EEPROM at address 4095 (4K words) and transfer each word to the same address in main system memory. More simply, mirror the BIOS into memory.
Decrement the address and repeat until reached address 0.
Reboot into main memory with the BOOTMODE = 0 instruction. The 2SBL payload which was loaded into memory will now execute.
Or,
{CORE RESETS INTO MEMORY REGION = 0b01, 1SBL BOOT ROM.}
{INITIALIZE ALL CORE REGISTERS TO ZERO.}
IF (STATUS.DIAG_BOOT = 1)
{ENTER DIAGNOSTIC BOOT MODE UNTIL RESET.}
ELSE
FOR (I = 4095; I >= 0; I--)
$R.1 = MEMORY(REGION = 0b10 (LPB Bus), DEVADDR = 0x03 (2SBL), ADDR = I);
MEMORY(REGION = 0b00 (Main Memory), ADDR = I) = $R.1;
END FOR;
REBOOT, REGION = 0b00 (Main Memory).
END IF;
It’s formatted that way because it’s basically VHDL syntax - I can just drop that into a .vhd file and it will synthesize.
Writing machine code by hand also makes you realize things that need adjusted:
Replaced LIT.H and LIT.L targets with a single 2-cycle instruction to do a full width load of the immediately following 16-bit word into LIT.Y.
There are several dozen more source files (27 right now and counting) for things like all the bus devices, clock/reset management, I/O buffers, etc. I suspect nobody cares about the eight bytes of ROM that’s just the CPUID and revision hanging off the system bus.
Been sidetracked by finishing a bathroom remodel, but I’m doing a huge update to get everything compiled into an actually readable blob of information - work on the project is picking back up now, so more to follow. I’m going to link an entirely new thread with everything nicely laid out and let this one die once that happens.
To anyone wondering what happened to the Dev Log that Wendell mentioned, the site is parked right now since I ran out of Linode credit, but I’m putting together a small system right now (it’s… well, it’s a cash register running Arch) to host it under my own power for anyone interested in it.
Hmm… I could, I’ll have to look into it. I didn’t really think of that one. I’ll definitely want to get a v1.0 of the architecture finalized and tested in hardware first with A) an actual memory management unit, and B) a formalized system bus interface, so that the core itself can evolve without completely obsoleting the entire rest of the system. It’s very much in a proof-of-concept state right now, which the good part is that I think it’s going great, it just has a long way to go before it’s at that point.
I hope to make that happen within the near future so that next Devember’s project can be writing an assembler and then compiler for this monstrosity.
Thanks for the update! I did wonder what had happened to the website so looking forward to something being put up again. I also ran fowl of FPGA’s going bye-bye at some point last year. Mouser is sitting on about $400 of my cash for some Intel/Altera parts that were slated for a software defined radio. Ticket still says delivery unknown and they’re not taking new orders
I only had two Altera Flex III FPGAs. But, I’ve found and bought a NOS case of Xilinx XC3000A-series FPGAs. These are between 3000 and 5000 gates, and around 300 registers/bits per FPGA. I think they were released sometime around 1996 nope, 1992, based on the original XC3000 from 1988. I’m planning on actually using them.
It’s been a nightmare to just track down the last software to support these, and then to get it running on literally anything. I seem to have it working as designed on Windows 2000, which is surprising given that it’s a native DOS program with support for Win95 at max. For anyone interested, it’s Xilinx Foundation, versions up to 2.1i. Any version of Foundation 2.1i use a software license key… XACTStep (only supports DOS/Win3.1) supports the XC3000A, but only with a hardware license dongle which simply no longer exists.
It’ll take ten of these things instead of one modern gate array to get the whole thing working, but I think it’s going to work, and I’ve got so many (and they’re just socketed, and configure from an external EEPROM) that quantity is kinda moot.
Here’s an option. Look up Altera MAX UP2 edu kit on eBay. They are super reasonably priced and have a pretty darn large FPGA and CPLD on it. I have half a dozen of these boards.
I actually really like these ancient little FPGAs. They just need something that resembles +5V, and configure from anything that even remotely functions as an 8-bit parallel storage device… the tsetup requirement is two thousand nanoseconds. You can even chain an arbitrary number of them together and they will configure each other as long as the configuration ROM has enough storage. The logic is just… smol.
Xilinx Foundation 1.5 (what I have) does technically support VHDL and ABEL (Hah, remember that one? 'Cause I don’t, it predates me), but the best way to build a design is realistically just to use the schematic entry tools. And man, does it feel unnatural when I’ve used VHDL for my entire professional career.
Getting the project back on track, big update coming Soon™ - have been learning about hosting a wiki on MediaWiki to present all of the information being generated by the project in a searchable manner, and I think it’s turning out pretty well.
It’s looking pretty good, but I need to do some more work on the general content and then getting it securely internet-facing before it’s ready for showtime. Wiki setup/configuration be interesting content for some of Wendell’s ‘Preserving Knowledge’ threads, too.
I’ll definitely want to get a v1.0 of the architecture finalized and tested in hardware first with A) an actual memory management unit, and B) a formalized system bus interface, so that the core itself can evolve without completely obsoleting the entire rest of the system. It’s very much in a proof-of-concept state right now, which the good part is that I think it’s going great, it just has a long way to go before it’s at that point.
