------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ ---- Project: NULL STAR (Devember 2021) ---- ---- Module: Execution Core ---- ---- Drawing: (Not Assigned) ---- ---- ---- ---- Filename: execution_core.vhd ---- ---- File Type: VHDL (93) ---- ---- Modified: 12/10/2021 ---- ---- Target: Universal ---- ---- Toolchain: Universal ---- ---- ---- ---- Dependencies: ---- ---- [ ] - stack.vhd ---- ---- ---- ---- Description: ---- ---- ---- ---- Revision History: ---- ---- 11/01/2021 - MDC - Initial release. ---- ---- 12/10/2021 - MDC - Replaced system memory bus implementation. ---- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity execution_core is port ( -- System Clock, Reset MCLK : in std_ulogic; MRST : in std_ulogic; -- Memory Bus Interface BUS_ADDRESS : out std_ulogic_vector(63 downto 0); BUS_REGION : out std_ulogic_vector(1 downto 0); BUS_DATA_IN : in std_ulogic_vector(15 downto 0); BUS_DATA_OUT : out std_ulogic_vector(15 downto 0); BUS_REQUEST_READ : out std_ulogic; BUS_REQUEST_WRITE : out std_ulogic; BUS_READY : in std_ulogic; -- Interrupt Controller Interface INTERRUPT : in std_ulogic; INTERRUPT_IDENT : in std_ulogic_vector(15 downto 0); INTERRUPT_ACK : out std_ulogic ); end entity execution_core; architecture Dataflow of execution_core is -- Control Flow ----------------------------------------------------------------------------------------------------- type core_control_state_T is (STATE_FETCH_START, STATE_FETCH_HOLD, STATE_EXECUTE, STATE_LOAD_START, STATE_LOAD_HOLD, STATE_LOAD_DONE, STATE_STORE_START, STATE_STORE_HOLD, STATE_STORE_DONE, STATE_BRANCH_CHECK, STATE_BRANCH_VALID, STATE_ENTER_ISR, STATE_EXIT_ISR, STATE_ENTER_SUBROUTINE, STATE_EXIT_SUBROUTINE, STATE_CHANGE_BOOT_MODE); signal core_control_state : core_control_state_T; signal select_program_counter : std_ulogic_vector(2 downto 0); signal select_interrupt_in_isr : std_ulogic_vector(1 downto 0); signal select_load_data : std_ulogic; signal select_target_enable : std_ulogic; signal select_bus_region : std_ulogic; signal select_BUS_ADDRESS : std_ulogic; alias instruction_source : std_ulogic_vector(7 downto 0) is BUS_DATA_IN(15 downto 8); alias instruction_target : std_ulogic_vector(7 downto 0) is BUS_DATA_IN(7 downto 0); signal writeback_bus : unsigned(15 downto 0); signal control_branch_requested : std_ulogic; signal control_branch_taken : std_ulogic; signal control_change_boot_mode : std_ulogic; signal control_request_load : std_ulogic; signal control_request_store : std_ulogic; signal control_enter_subroutine : std_ulogic; signal control_exit_subroutine : std_ulogic; signal control_exit_isr : std_ulogic; signal control_interrupt_active : std_ulogic; signal bus_region_default : std_ulogic_vector(1 downto 0); --------------------------------------------------------------------------------------------------------------------- -- Program Counter -------------------------------------------------------------------------------------------------- signal program_counter_D, program_counter_Q : unsigned(63 downto 0); signal stack_top : std_ulogic_vector(63 downto 0); signal stack_push : std_ulogic; signal stack_pop : std_ulogic; signal stack_full : std_ulogic; signal stack_empty : std_ulogic; signal stack_pointer : std_ulogic_vector(4 downto 0); --------------------------------------------------------------------------------------------------------------------- -- Registers -------------------------------------------------------------------------------------------------------- signal register_add_a_Q : unsigned(16 downto 0); signal register_add_b_Q : unsigned(16 downto 0); signal register_negate_a_Q : unsigned(15 downto 0); signal register_and_a_Q : unsigned(15 downto 0); signal register_and_b_Q : unsigned(15 downto 0); signal register_or_a_Q : unsigned(15 downto 0); signal register_or_b_Q : unsigned(15 downto 0); signal register_invert_a_Q : unsigned(15 downto 0); signal register_xnor_a_Q : unsigned(15 downto 0); signal register_xnor_b_Q : unsigned(15 downto 0); signal register_sll_operand_Q : unsigned(15 downto 0); signal register_sll_magnitude_Q : unsigned(3 downto 0); signal register_srl_operand_Q : unsigned(15 downto 0); signal register_srl_magnitude_Q : unsigned(3 downto 0); signal register_literal_Q : std_ulogic_vector(15 downto 0); signal register_gpreg_7_Q : unsigned(15 downto 0); signal register_gpreg_6_Q : unsigned(15 downto 0); signal register_gpreg_5_Q : unsigned(15 downto 0); signal register_gpreg_4_Q : unsigned(15 downto 0); signal register_gpreg_3_Q : unsigned(15 downto 0); signal register_gpreg_2_Q : unsigned(15 downto 0); signal register_gpreg_1_Q : unsigned(15 downto 0); signal register_gpreg_0_Q : unsigned(15 downto 0); signal register_store_data_Q : unsigned(15 downto 0); signal register_global_address_Q : unsigned(63 downto 0); signal register_interrupt_vector_Q : unsigned(63 downto 0); signal register_interrupt_enable_Q : std_ulogic; signal register_memory_region_Q : std_ulogic_vector(1 downto 0); signal register_boot_mode_Q : std_ulogic; signal register_load_data_D, register_load_data_Q : std_ulogic_vector(15 downto 0); signal register_interrupt_in_isr_D, register_interrupt_in_isr_Q : std_ulogic; signal register_core_status_D, register_core_status_Q : std_ulogic_vector(15 downto 0); signal result_add_D, result_add_Q : unsigned(16 downto 0); signal result_negate_D, result_negate_Q : unsigned(15 downto 0); signal result_and_D, result_and_Q : unsigned(15 downto 0); signal result_or_D, result_or_Q : unsigned(15 downto 0); signal result_invert_D, result_invert_Q : unsigned(15 downto 0); signal result_xnor_D, result_xnor_Q : unsigned(15 downto 0); signal result_srl_D, result_srl_Q : unsigned(15 downto 0); signal result_sll_D, result_sll_Q : unsigned(15 downto 0); --------------------------------------------------------------------------------------------------------------------- begin -- Concurrent Assignments ------------------------------------------------------------------------------------------- BUS_DATA_OUT <= std_ulogic_vector(register_store_data_Q); bus_region_default <= '0' & register_boot_mode_Q; --------------------------------------------------------------------------------------------------------------------- -- Execution Results ------------------------------------------------------------------------------------------------ result_add_D <= unsigned(signed(signed(register_add_a_Q) + signed(register_add_b_Q))); result_negate_D <= unsigned(signed(0 - signed(register_negate_a_Q))); result_and_D <= register_and_a_Q and register_and_b_Q; result_or_D <= register_or_a_Q or register_or_b_Q; result_invert_D <= not register_invert_a_Q; result_xnor_D <= register_xnor_a_Q xnor register_xnor_b_Q; result_srl_D <= unsigned(register_srl_operand_Q srl to_integer(register_srl_magnitude_Q)); result_sll_D <= unsigned(register_sll_operand_Q sll to_integer(register_sll_magnitude_Q)); register_core_status_D(15 downto 11) <= stack_pointer; register_core_status_D(10 downto 4) <= (others => '0'); register_core_status_D(3) <= INTERRUPT; register_core_status_D(2) <= stack_full; register_core_status_D(1) <= stack_empty; register_core_status_D(0) <= result_add_Q(16); --------------------------------------------------------------------------------------------------------------------- -- Source Decode ---------------------------------------------------------------------------------------------------- with instruction_source select writeback_bus <= x"0000" when x"00", result_add_Q(15 downto 0) when x"01", result_negate_Q when x"02", result_and_Q when x"03", result_or_Q when x"04", result_invert_Q when x"05", result_xnor_Q when x"06", result_sll_Q when x"07", result_srl_Q when x"08", unsigned(register_literal_Q) when x"09", register_gpreg_7_Q when x"0A", register_gpreg_6_Q when x"0B", register_gpreg_5_Q when x"0C", register_gpreg_4_Q when x"0D", register_gpreg_3_Q when x"0E", register_gpreg_2_Q when x"0F", register_gpreg_1_Q when x"10", register_gpreg_0_Q when x"11", unsigned(register_load_data_Q) when x"12", unsigned(INTERRUPT_IDENT) when x"13", unsigned(register_core_status_Q) when x"14", x"FFFF" when x"FF", x"0000" when others; --------------------------------------------------------------------------------------------------------------------- -- Target Decode ---------------------------------------------------------------------------------------------------- Target_Decode_Sync_Process : process (MCLK) begin if rising_edge(MCLK) then if (MRST = '1') then register_store_data_Q <= x"0000"; register_memory_region_Q <= "00"; register_boot_mode_Q <= '1'; register_interrupt_enable_Q <= '0'; elsif (select_target_enable = '1') then case instruction_target is when x"00" => null; -- NULL when x"01" => register_add_a_Q <= '0' & writeback_bus; when x"02" => register_add_b_Q <= '0' & writeback_bus; when x"03" => register_negate_a_Q <= writeback_bus; when x"04" => register_and_a_Q <= writeback_bus; when x"05" => register_and_b_Q <= writeback_bus; when x"06" => register_or_a_Q <= writeback_bus; when x"07" => register_or_b_Q <= writeback_bus; when x"08" => register_invert_a_Q <= writeback_bus; when x"09" => register_xnor_a_Q <= writeback_bus; when x"0A" => register_xnor_b_Q <= writeback_bus; when x"0B" => register_srl_operand_Q <= writeback_bus; when x"0C" => register_srl_magnitude_Q <= writeback_bus(3 downto 0); when x"0D" => register_sll_operand_Q <= writeback_bus; when x"0E" => register_sll_magnitude_Q <= writeback_bus(3 downto 0); when x"0F" => register_literal_Q(7 downto 0) <= instruction_source; when x"10" => register_literal_Q(15 downto 8) <= instruction_source; when x"11" => register_gpreg_0_Q <= writeback_bus; when x"12" => register_gpreg_1_Q <= writeback_bus; when x"13" => register_gpreg_2_Q <= writeback_bus; when x"14" => register_gpreg_3_Q <= writeback_bus; when x"15" => register_gpreg_4_Q <= writeback_bus; when x"16" => register_gpreg_5_Q <= writeback_bus; when x"17" => register_gpreg_6_Q <= writeback_bus; when x"18" => register_gpreg_7_Q <= writeback_bus; when x"19" => register_global_address_Q(15 downto 0) <= writeback_bus; when x"1A" => register_global_address_Q(31 downto 16) <= writeback_bus; when x"1B" => register_global_address_Q(47 downto 32) <= writeback_bus; when x"1C" => register_global_address_Q(63 downto 48) <= writeback_bus; when x"1D" => null; -- LOAD when x"1E" => register_store_data_Q <= writeback_bus; when x"1F" => null; -- JUMP when x"20" => null; -- BRANCH ON ZERO when x"21" => null; -- BRANCH ON CARRY when x"22" => null; -- ENTER SUBROUTINE when x"23" => null; -- EXIT SUBROUTINE when x"24" => register_interrupt_vector_Q(15 downto 0) <= writeback_bus; when x"25" => register_interrupt_vector_Q(31 downto 16) <= writeback_bus; when x"26" => register_interrupt_vector_Q(47 downto 32) <= writeback_bus; when x"27" => register_interrupt_vector_Q(63 downto 48) <= writeback_bus; when x"28" => register_interrupt_enable_Q <= writeback_bus(0); when x"29" => null; -- EXIT ISR when x"2A" => register_memory_region_Q <= std_ulogic_vector(writeback_bus(1 downto 0)); when x"2B" => register_boot_mode_Q <= writeback_bus(0); when others => null; end case; end if; end if; end process Target_Decode_Sync_Process; --------------------------------------------------------------------------------------------------------------------- -- Core Registers --------------------------------------------------------------------------------------------------- Register_Sync_Process : process (MCLK) begin if rising_edge(MCLK) then -- Reset if (MRST = '1') then program_counter_Q <= (others => '0'); else program_counter_Q <= program_counter_D; end if; -- Free Running result_add_Q <= result_add_D; result_negate_Q <= result_negate_D; result_and_Q <= result_and_D; result_or_Q <= result_or_D; result_invert_Q <= result_invert_D; result_xnor_Q <= result_xnor_D; result_srl_Q <= result_srl_D; result_sll_Q <= result_sll_D; register_load_data_Q <= register_load_data_D; register_interrupt_in_isr_Q <= register_interrupt_in_isr_D; register_core_status_Q <= register_core_status_D; end if; end process Register_Sync_Process; --------------------------------------------------------------------------------------------------------------------- -- Core Control FSM Conditions -------------------------------------------------------------------------------------- control_branch_requested <= '1' when ((instruction_target = x"21") -- Branch on Zero or (instruction_target = x"20") -- Branch on Carry or (instruction_target = x"1F")) -- Jump else '0'; control_branch_taken <= '1' when ((writeback_bus = x"0000_0000") -- Branch on Zero or (register_core_status_Q(0) = '1') -- Branch on Carry or (instruction_target = x"1F")) -- Jump else '0'; control_change_boot_mode <= '1' when (instruction_target = x"2B") else '0'; control_interrupt_active <= '1' when ((INTERRUPT = '1') and (register_interrupt_enable_Q = '1') and (register_interrupt_in_isr_Q = '0')) else '0'; control_request_load <= '1' when (instruction_target = x"1D") else '0'; control_request_store <= '1' when (instruction_target = x"1E") else '0'; control_exit_isr <= '1' when (instruction_target = x"29") else '0'; control_enter_subroutine <= '1' when (instruction_target = x"22") else '0'; control_exit_subroutine <= '1' when (instruction_target = x"23") else '0'; --------------------------------------------------------------------------------------------------------------------- -- Address Stack Instance ------------------------------------------------------------------------------------------- Address_Stack_Instance : entity work.stack generic map ( ADDR_WIDTH => 5, DATA_WIDTH => 64 ) port map ( MCLK => MCLK, MRST => MRST, DATA_IN => std_ulogic_vector(program_counter_Q), DATA_OUT => stack_top, RD_EN => stack_pop, WR_EN => stack_push, STATUS_EMPTY => stack_empty, STATUS_FULL => stack_full, STATUS_PTR => stack_pointer ); --------------------------------------------------------------------------------------------------------------------- -- Datapath Control Decode ------------------------------------------------------------------------------------------ with select_program_counter select program_counter_D <= program_counter_Q when "000", -- Stall Program Counter program_counter_Q + 1 when "001", -- Increment Program Counter register_global_address_Q when "010", -- Jump to Global Address Register register_interrupt_vector_Q when "011", -- Jump to Interrupt Vector unsigned(stack_top) when "100", -- Jump to Stack Top (others => '0') when "101", -- Return to Address Zero (others => 'X') when others; with select_interrupt_in_isr select register_interrupt_in_isr_D <= register_interrupt_in_isr_Q when "00", -- Hold ISR Status '0' when "01", -- Clear ISR Active '1' when "10", -- Set ISR Active 'X' when others; with select_load_data select register_load_data_D <= register_load_data_Q when '0', -- Hold Load Data Register BUS_DATA_IN when '1', -- Latch MBUS_DATA_IN into Load Data Register (others => 'X') when others; with select_bus_region select BUS_REGION <= bus_region_default when '0', register_memory_region_Q when '1', (others => 'X') when others; with select_BUS_ADDRESS select BUS_ADDRESS <= std_ulogic_vector(program_counter_Q) when '0', -- Program Counter Presented on Bus std_ulogic_vector(register_global_address_Q) when '1', -- Global Address Register Presented on Bus (others => 'X') when others; --------------------------------------------------------------------------------------------------------------------- -- Core Control FSM ------------------------------------------------------------------------------------------------- Core_Control_FSM_Sync_Process : process (MCLK) begin if rising_edge(MCLK) then if (MRST = '1') then core_control_state <= STATE_CHANGE_BOOT_MODE; else case core_control_state is when STATE_FETCH_START => if (control_interrupt_active = '1') then core_control_state <= STATE_ENTER_ISR; elsif (BUS_READY = '1') then core_control_state <= STATE_FETCH_HOLD; else core_control_state <= STATE_FETCH_START; end if; when STATE_FETCH_HOLD => if (BUS_READY = '1') then if (control_branch_requested = '1') then core_control_state <= STATE_BRANCH_CHECK; elsif (control_request_load = '1') then core_control_state <= STATE_LOAD_START; elsif (control_request_store = '1') then core_control_state <= STATE_STORE_START; elsif (control_enter_subroutine = '1') then core_control_state <= STATE_ENTER_SUBROUTINE; elsif (control_exit_subroutine = '1') then core_control_state <= STATE_EXIT_SUBROUTINE; elsif (control_exit_isr = '1') then core_control_state <= STATE_EXIT_ISR; elsif (control_change_boot_mode = '1') then core_control_state <= STATE_CHANGE_BOOT_MODE; else core_control_state <= STATE_EXECUTE; end if; else core_control_state <= STATE_FETCH_HOLD; end if; when STATE_EXECUTE => core_control_state <= STATE_FETCH_START; when STATE_LOAD_START => if (BUS_READY = '1') then core_control_state <= STATE_LOAD_HOLD; else core_control_state <= STATE_LOAD_START; end if; when STATE_LOAD_HOLD => if (BUS_READY = '1') then core_control_state <= STATE_LOAD_DONE; else core_control_state <= STATE_LOAD_HOLD; end if; when STATE_LOAD_DONE => core_control_state <= STATE_FETCH_START; when STATE_STORE_START => if (BUS_READY = '1') then core_control_state <= STATE_STORE_HOLD; else core_control_state <= STATE_STORE_START; end if; when STATE_STORE_HOLD => if (BUS_READY = '1') then core_control_state <= STATE_STORE_DONE; else core_control_state <= STATE_STORE_HOLD; end if; when STATE_STORE_DONE => core_control_state <= STATE_FETCH_START; when STATE_BRANCH_CHECK => if (control_branch_taken = '1') then core_control_state <= STATE_BRANCH_VALID; else core_control_state <= STATE_EXECUTE; end if; when STATE_BRANCH_VALID => core_control_state <= STATE_FETCH_START; when STATE_ENTER_ISR => core_control_state <= STATE_FETCH_START; when STATE_EXIT_ISR => core_control_state <= STATE_FETCH_START; when STATE_ENTER_SUBROUTINE => core_control_state <= STATE_FETCH_START; when STATE_EXIT_SUBROUTINE => core_control_state <= STATE_FETCH_START; when STATE_CHANGE_BOOT_MODE => core_control_state <= STATE_FETCH_START; when others => core_control_state <= STATE_FETCH_START; end case; end if; end if; end process Core_Control_FSM_Sync_Process; Core_Control_FSM_Output_Process : process (core_control_state) begin case core_control_state is when STATE_FETCH_START => BUS_REQUEST_READ <= '1'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_FETCH_HOLD => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_EXECUTE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "001"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '1'; stack_push <= '0'; stack_pop <= '0'; when STATE_LOAD_START => BUS_REQUEST_READ <= '1'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_LOAD_HOLD => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_LOAD_DONE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "001"; select_interrupt_in_isr <= "00"; select_load_data <= '1'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_STORE_START => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '1'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_STORE_HOLD => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_STORE_DONE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '1'; select_BUS_ADDRESS <= '1'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_BRANCH_CHECK => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_BRANCH_VALID => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "010"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when STATE_ENTER_ISR => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "011"; select_interrupt_in_isr <= "10"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '1'; stack_pop <= '0'; when STATE_EXIT_ISR => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '1'; select_program_counter <= "100"; select_interrupt_in_isr <= "01"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '1'; when STATE_ENTER_SUBROUTINE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "010"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '1'; stack_pop <= '0'; when STATE_EXIT_SUBROUTINE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "100"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '1'; when STATE_CHANGE_BOOT_MODE => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "101"; select_interrupt_in_isr <= "01"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; when others => BUS_REQUEST_READ <= '0'; BUS_REQUEST_WRITE <= '0'; INTERRUPT_ACK <= '0'; select_program_counter <= "000"; select_interrupt_in_isr <= "00"; select_load_data <= '0'; select_bus_region <= '0'; select_BUS_ADDRESS <= '0'; select_target_enable <= '0'; stack_push <= '0'; stack_pop <= '0'; end case; end process Core_Control_FSM_Output_Process; --------------------------------------------------------------------------------------------------------------------- end architecture Dataflow;