4.5Ghz water and 5.0GHz chilled 7980XE is doable today and frankly not very hard in their respective domains. 4.5Ghz all-core is actually my daily-driver config here @1.175v core voltage (under water - not chilled). I use -5 and -7 offsets for AVX and AVX512.
The larger socket has greater power provision and 7980XE (and the 8180 likely/suspected for that demo) are Skylake silicon. So, better/greater power provision in the socket and better silicon process might make this more viable than you think. (but yes, its still 10 more cores…)
I think you are looking at a 500-600W CPU in a ~250W socket under the best of circumstances. From an overclocker’s perspective 300-400W in a 150-180W socket is not “unreasonable”, but linearly scaling that to 500-600W definitely brings this into new/concerning territory. x299 has been more limited by VRM cooling than the socket/pin melting even in the 400-500W range (none of which I’ve actually seen - only worried about).
p.s. none of that means I am not very seriously considering a 32 core TR regardless of what Intel brings out. Waiting to see some hard numbers. 32 cores at 4.0GHz with reasonable cooling is very attractive relative to 28 cores at 4.5 with much more exotic cooling.
It took Intel running a chiller to get the 28 core at 5GHZ for Cinnebench, which with more tinkering you might have gotten some Prime 95 but obviously didn’t want to push it with Prime 95 otherwise they would have made it part of their presentation.
I think the scaling is going to bite Intel in the ass with this one. Your 7980 is 10 cores less, can’t really compare that to this 28 core part. To increase power necessary to run those extra 10 cores at a high clock while dissipating the heat is a tough ask. Physics is a bitch.
I suspect 32 core will probably come down to silicon lottery at about 3.8 and above with good cooling. But 32 cores @ 3.8 is pretty fuckin awesome considering the fact that kind of performance costs will be very reasonable versus a 28 core behemoth that requires exotic cooling to get close to its performance potential (and 850 to 1000 motherboard).
This is why the Intel part doesn’t excite me… because its bullshit. They started off the presentation with bullshit, showed bullshit then after said oh our presenter forgot to mention it was overclocked. Seriously… a presenter for Intel is going to go off script and “forget” its overclocked. Again, more bulshit. Meanwhile AMD is like ok… here is 32 cores, here is the air cooler, and we’ll take orders in August. Much different presentation, one in reality… other not so much.
Counting on it - see larger socket and improved si in my assumptions. There’s a fair amount of “back-of-envelope” in my assertions, but there is also a deep familiarity OCing lots of HW (X and Xeon), Broadwell and SKylake chips. 5.0GHz at the core level isn’t much of a stretch. For SKL-X/P that tended to require ~1.35v. The real issue was not the cores, but the overall package power delivery.
4.5GHz is even more of a yawn at the core level <1.20v
OK, so if its not a stretch why run it on a chiller? You keep saying its not a problem, not a stretch but they ran in on a chiller with ozone killing refrigerant. Larger package is only going to get so far. They bullshitted this presentation as a 28 core, 5GHZ part… it ain’t a fuckin 5GHZ part, with special cooling and delidding it’ll probably plop down at 4.5 to 4.7(higher if you win the silicon lottery) under real workloads, “regular cooling” maybe 4.2 with a silicon lottery win.
To make these chips look better they may bin the living shit out of them… which would certainly help the consumer. I guess if you are going to spend what will probably be 4 to 6000k for the chip, 850 to 1000 motherboard then the cooling solution which probably will require a minimum 250 dollar investment you should get the best of the best. Again this is why this part doesn’t excite me, its past the bleeding edge of technology.
WRT my statements, keep 4.5 and 5.0GHz in perspective and separate - they are two very different thresholds for anything SKYLX to be sure… 4.4-4.5 is the “knee in the curve” so going beyond is steep exponential in voltage and thus power. I expect the improved silicon to have a little more head-room/efficiency.
THEY used a chiller to hit 5.0GHz just I would to get my 7980XE to do the same. Without it even 4.7 all-core is well into the high 80C range on water. I need a chiller to hit 5.0GHz all-core on a 7980XE.
I am not trying to justify their demo/deception. It frankly showed me nothing I couldn’t already work out on the backs of those envelopes from what I’ve seen. God-mode silicon binning (golden chip) SKL has no trouble running 5.0GHz on many/all cores. If you can give it power and keep it cool (see chiller), the chip and the socket looked like it could sustain those powers. Their demo was BS. No excuses for what they did there. It was designed to deceive… it deceived…
My point was that it was not as far away from what could be delivered to the HEDT as some have made it sound if you set a more “realistic” goal of ~4.5GHz OC rather than 5.0GHz. (non-AVX)
As per my prior post - AMD’s power consumption and compute power at ~4.0GHz (more cores) is a compelling argument against Intel chips that potentially exceed the AMD chips in head-line benchmarks but at 50-100% more wattage (with corresponding de-lid and cooling issues). There too from TR1, 4.0GHz may require binning and or custom-loop water, but should be achievable given what we’ve seen from the 2xxxx series so far.
The demo AMD run at computex was done on air. They didn’t show clock speeds of course but 4GHz all core would already have been an OC on first gen. I would guess XFR2 is gonna keep the clocks pretty high if possible and not many workloads can actually completely peg 64 threads.
250W max at stock on a heatspreader of that size shouldn’t be a big deal. Put a Noctua on and it’s fine.
All of this is why I cannot say that what Intel is offering is actually exciting… a cannibalized server part hastily thrown together in a complete bullshit demonstration where not only did Intel lie about the capability they went above and beyond to mask their “new” part. AMD’s is exciting, only thing that could be considered exciting about Intel’s is just how exciting of a shitshow is the actual part going to be. And trolling Intel, that could be exciting too.
TR2 will still be 4 channel, however the extra two dies will indirectly access the 4 channels of memory via infinity fabric -> other CPU memory bus. Which is how half of the memory is accessed in a version 1 threadripper anyway - you only get 2 channels per die directly, the “other” channels are accessed via the other die via infinity fabric.
Which will be interesting to see how it works… may require some trickery in optimisation to ensure that threads needing to stream a lot of data are pinned to cores with direct connection to the memory, and threads that are tight loops and can fit in CPU cache are biased towards the cores on the other two dies.
I’m sure AMD have done their homework to ensure that even though its not as good as 8 channel epyc, its still better overall than dual die threadripper even with the memory bus contention.
