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The RYZEN 1000 Thread! Summit Ridge - General Discussion



Does anyone know if the new 2200g and 2400 g APUs have the 4k decode DRM on chip. Like can they do Amazon and Netflix at 4k and run that pioneer 4k blu ray drive?


Yes they can. I don’t know about DRM for this context. Buy they can hardware decode 4K just fine.

OK just checked and this article confirms it will be made available with even more features in future.


Well, thread title says anything, so here it is:

I modeled and rendered my 2400G in Fusion 360 as part of a self-challenge to 3D model one thing per day (which I’ll be doing in Fusion and SolidWorks depending, and might take up Inventor if I get the urge).

Regular screenshots of the model:


Well this is interesting if true, at least from an academic perspective (I won’t be buying one no matter what’s in it):

I think we need an “ANYTHING ON RYZVEGA” thread…


The Ryzen V1000 series is really something special

AMD went full murder mode on the embedded X86 SoC market.


WOW, 10GE incoming! Nice.
The V1605B looks nuts on paper, I gotta say.


That would be really nice if you already got a video card and want to do win vm.


Steve got himself a boot kit.


I found it a little annoying that he didn’t bring up that Intel had the same issue with Kaby Lake and did nothing.


Something that’s been bugging me, and hopefully it’s a simple answer so I can move on with my life:

Why does pcie lane splitting (x16 vs x8/x8) depend on the chipset (X370 vs. B350, e.g.) The lanes come from the cpu; why would the switch live on the chipset?

Is it just a marketing method to create separation between X370 and B350 products? Why not allow for further splits (x8/x4/x4 or x4/x4/x4/x4) and give motherboard manufacturers the freedom to make interesting products?


Switches: Since PCI Express is a point-to-point serial interconnect standard, it requires a switch to connect a single PCI Express port from a processor or chipset to multiple end-points. PLX started with the PCIe 1.0 family at 2.5 Gigatransfers per second in 2004, followed by PCIe 2.0 products in late 2007, where the data rate doubled to 5.0 Gigatransfers per second.[2] The company offers more than 18 PCIe 3.0 products at 8 Gigatransfers per second. Such chips can be optionally installed by motherboard manufacturers to increase the number of available PCIe lanes.


Close, but not entirely satisfactory. I do know of the existence of PLX switches.
Specifically in the case of Ryzen, is there a PLX switch integrated into the X370 chipset?


This does help drive the point home that mobo manufacturers do have the freedom to make more interesting products via the addition of more PLX switches. I am reminded now of some of ASUS X-99 WS boards…or maybe X-299 WS that had a couple extra PLX switches. I used to drool over the idea of having one of those.

Thanks :slight_smile:


Exactly, point is that the motherboard manufacturers can chose to make different boards for different needs. Designing and manufacturing each new design is costly enough that without sufficient perceived demand most MoBo designers will rather not go that rout and instead create something generic.


so, just for my full understanding:
the x16 lanes go through the chipset (on a separate run from the 3.0 x4 “DMI”) hit some sort of integrated PLX switch (if it’s there) and then run over to the physical interface slots?

or does AMD throw in a free PLX switch for every X370 chipset that’s ordered by the mobo manufacturers and it just lives somewhere on the mobo?


PCI Express is a serial connection that operates more like a network than a bus. Instead of one bus that handles data from multiple sources, PCIe has a switch that controls several point-to-point serial connections. (See How LAN Switches Work for details.) These connections fan out from the switch, leading directly to the devices where the data needs to go. Every device has its own dedicated connection, so devices no longer share bandwidth like they do on a normal bus. We’ll look at how this happens in the next section.

This is just from end of page 1. 5 pages total. Enjoy the read.


I’m not getting my question across clearly enough, because said article does not answer the question.
Let’s say there are two motherboards with identical PCIe physical slot layouts including two x16 physical slots.

One board has an X370 chipset. One board has a B350 chipset.

Considering that there are x16 lanes coming from the Ryzen CPU in both cases, what is the limitation that prevents the B350 board from being wired x8/x8 the way the X370 board can be?

I.e. does the PCIe switch live on the CPU or on the chipset? Or somewhere else on the board?


So X370 gets 8 general purpose PCIe slots and B350 gets 6. Far as I can tell it is up to mobo maker to decide how to split them up. These are 2.0 btw.

Only the CPU offers PCIe 3.0.

The AM4 motherboards equipped with the B350 and X370 chipsets that feature two PCI-E x16 expansion slots will run as x8 in each slot in a dual GPU setup. (In a single GPU setup, the top slot can run at full x16 speeds.) Which is to say that the slots behave the same across both chipsets. Where the chipsets differ is in support for specific GPU technologies where NVIDIA’s SLI is locked to X370.

If you mean for SLI then NVidia requiring minimum of X8 per each GPU and likely related licensing costs.


Anybody have experience both from Precision Boost & 2, asking because I wonder if that refresh would allow more aimed overclocks, and maybe even choosing which cores can do what


Have already read and watched. Doesn’t help me understand what I’m looking for.
Thanks for your efforts, though.

I’m looking for how the chipset (or the CPU’s knowledge of which chipset it is connected to) affects the way the pcie root complex operates on the CPU. If the x8/x8 split happens in the ‘uncore,’ it theoretically does not have to depend on the chipset.