PFF you think I’d have time to dig up hardware enough FOR a store?
tho an online shop selling modded powerbook G4’s mith linux on them could be… Interesting.
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No, not really (on the time). I would just love to see some stuff circulating that came from someone, that I was sure they weren’t talking out their ass. Beyond that somewhere (someone) for you to unload one project, to move on to the next. And get this awesome content you keep providing along the way. You always post content right up my alley, that makes me say, I wish I had a little more time, money, knowledge, hell, ROOM for the next project. I have been getting kinda burnout on “mainstream”, that was never really my thing to begin with. Really just got back into anything computer related, after more than a 10 year hiatus.
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Gotta keep it creative I mean…
I started doing so much weird shit because most everyone that had a project on here was so poindexter about it. The most creative one was a gaming pc with a titan in a suitcase.
FFS I thought people would have more interest in demoscene than this but I guess not.
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Nice to see it up finally!
Though Linus does confuse the specs a bit, when he’s describing chips, he says all the chips have 44 PCIe lanes; since he mentions quad channel, you can assume he’s specifically talking about Sforza, but Sforza has 48 PCIe lanes, not 44.
Not that I really blame him, the chip vs module vs scale up/out differences can be confusing.
I’ve made myself an LTT account to post on their forum, hopefully I’ll get a response from Dylanc1500 (he claims to have gotten Portal 2 running on POWER9).
Its a good os. I’m hoping to have it on a few machines pelmanently in the next few months
I heard this stuff does FreeBSD. So, what should I buy?
Info links for FreeBSD on POWER9
The FreeBSD support is still sort of in the works according to the Raptor community wiki:
https://wiki.raptorcs.com/wiki/Operating_System_Compatibility_List#BSDs
and FreeBSD’s own wiki:
https://wiki.freebsd.org/powerpc/POWER9
Official FreeBSD PowerPC page is not all that helpful:
https://www.freebsd.org/platforms/ppc.html
System advice
CPU
I’m not under any illusions of swimming in money, but I would still say to go for an 8-core if you can; since it’s the best per core value:
| Cores | Price (USD) | USD/core | L2/core | L3/core |
|---|---|---|---|---|
| 4 | 375 | ~94 | 512 KiB | 10 MiB |
| 8 | 595 | ~74 | 512 KiB | 10 MiB |
| 18 | 1425 | ~79 | 256 KiB | 5 MiB |
| 22 | 2625 | ~119 | 256 KiB | 5 MiB |
The L2 & L3 difference is because cache is shared between core pairs. The silicon is designed for 24 cores, so once you bin for less than 12 cores, you can disable only one half of each pair, but keep the full cache amount.
Bundles
They sell bundles that give a discount for mainboard+CPU or mainboard+CPU+heatsink. Unless you are jerry-rigging something custom for cooling, you will need the heatsink they sell.
The bundles represent what you minimally need, since cases, PSUs, and other components aren’t specific to POWER9. See:
https://wiki.raptorcs.com/wiki/Talos_II/Hardware_Compatibility_List
I’d love to see an unlocked xell vs like power7.
The latest Ask Noah podcast has an interview with Hugh Blemmings:
Among other anecdotes, he mentions a particular embedded use-case soldering a POWER8 CPU directly to the mainboard, rather than using a socket, due to high vibration being a concern. I wonder what that was.
Also nice to hear that OZLabs is “very much committed” to supporting bi-endian for the Linux kernel on Power.
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Huh, I hadn’t realized that Kolab was using OpenPOWER machines:
This video is more than two years old though, I wonder if anything’s changed since then; their speaker sounded fairly enthusiastic, but the Kolab Enterprise site curiously only mentions POWER8 not POWER9 on the Supported Platforms page:
Hardware Platforms
The Kolab server is available and certified for the OpenPOWER based IBM Power8, as well as for Intel x86 based hardware for primary and secondary platforms as far as these are certified for the hardware.
Well 8 is just as good
also why invest a billion bucks into a system you JUST integrated and are probably STILL testing.
It’s a software package though, not everyone will want to use the older POWER8 hardware if they are buying new, I’d think. It would be like a software package listing Zen as supported, but not Zen+.
Especially now with Talos II around, I think you’d be paying more for an older system unless you bought used, and I don’t see an enterprise customer doing that.
This topic was automatically opened after 5 hours.
Ortega Project Status
The reverse-engineered and clean-room re-implemented firmware for the BCM5719 Broadcom NICs used by Talos II and Blackbird is nearing completion.
Talospace has a short article, which links to a clean-room repo on GitHub, and an explanation/blog post from Hugo Landau (who did the reversing).
Context for newcomers to the thread:
The BCM5719 device firmware is the only remaining proprietary blob on all Blackbird/Talos II systems.
However, the Talos II’s optional SAS controller from MicroSemi does also need device firmware.
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Roadmap to POWER10
I keep seeing similar looking roadmap charts with minor changes between them, so I thought I would make a post here with what I find as most recent info:
| POWER9 SO | POWER9 SU | POWER9’ | POWER10 | |
|---|---|---|---|---|
| General Availability | 2017 | 2018 | 2019 | 2021+ |
| Cores | 12/24 | 12/24 | 12/24 | TBA |
| Lithography | Globalfoundries 14nm | Globalfoundries 14nm | Globalfoundries 14nm | Samsung 7nm |
| Marketing | New Micro-Architecture Direct Attach Memory New Process Technology |
Enhanced Micro-Architecture Buffered Memory |
Enhanced Micro-Architecture New Memory Subsystem |
New Micro-Architecture New Technology |
| Sustained memory bandwidth | 150 GB/s | 210 GB/s | 400 GB/s | 435+ GB/s |
| Standard I/O Interconnect | PCIe Gen4 x48 | PCIe Gen4 x48 | PCIe Gen4 x48 | PCIe Gen5 |
| Advanced I/O Signaling | 25 GT/s 300 GB/s |
25 GT/s 300 GB/s |
25 GT/s 300 GB/s |
32 & 50 GT/s |
| Advanced I/O Architecture | CAPI 2.0, OpenCAPI 3.0, NVLink 2.0 |
CAPI 2.0, OpenCAPI 3.0, NVLink 2.0 |
CAPI 2.0, OpenCAPI 4.0, NVLink 3.0 |
TBA |
I’m mainly using the 2018 October EU OpenPOWER Summit OpenCAPI presentation as a reference, but also adding info from a Jeff Stuechelli video saying 400 GB/s per socket, and POWER10 as “some time after 2020”.
IBM terminology
The suffixes used for revisions of POWER chips have specific meanings:
Plus sign +
a “plus” chip in the IBM lingo means something very precise, and that is usually a process shrink coupled with some slight microarchitecture changes
from NextPlatform article on new roadmap (April 2016)
Prime symbol ’
it designates a change in the I/O and possibly memory subsystems in a Power processor; it is distinct from a plus sign, which means a change in process or architecture or both in a Power chip, but well short of a major version which has big changes
from Nextplatform article on Samsung as POWER10 fab (December 2018)
Sources and past roadmaps
- 2016 April OpenPOWER Summit roadmap - NextPlatform article and IT Jungle article have same author
- 2018 Roadmap at Hot Chips - Anandtech article, HPCWire article (better image)
- 2018 October EU OpenPOWER Summit - from slide 12 of OpenCAPI and its Roadmap presentation
- 2018 December NextPlatform article on Samsung being the POWER10 fab contains two roadmaps, one from a 2018 OpenPOWER Summit (not sure which one though)
Because the OpenPOWER machines only use SMT4 chips, some roadmap charts intended for OpenPOWER audiences may say “24 cores” rather than “12/24 cores”.
However, it is entirely possible for OpenPOWER vendors to use the SMT8 chips, though they choose not to:
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Hmm… I wonder if that POWER9’ chip coming out this year in 2019 will be drop in compatible with existing boards? Am I reading your chart correctly @olddellian?
I am almost certain that no, it will not be. The main point of buying one of these would be to use OpenCAPI 4.0 or NVLink 3.0, which would probably need a board redesign anyway.
NextPlatform wrote last year about POWER9’ potentially using OpenCAPI to interface with OpenCAPI memory as an alternative to POWER9 SU using SerDes to talk with Centaur-buffered memory; this is potentially further incompatibility with POWER9 SO&SU boards. You can read about OpenCAPI memory here:
https://www.nextplatform.com/2018/08/28/ibm-power-chips-blur-the-lines-to-memory-and-accelerators/
Though I don’t really know all that much about these sockets. I never did get a reply about whether SO (Scale Out) and SU (Scale Up), even use the same physical sockets.
POWER8 vs POWER8’
From the RCS Wiki talk page on POWER8’ (listed there as POWER8E):
We have no direct experience with this module, aside from the fact that it does not work (or even fit) in the standard POWER8 socket.
Though that’s not a fair comparison, since POWER8 → POWER8’ added NVLink connections, whereas POWER9 → POWER9’ is only updating them.
TLDR
There are a bunch of questions here,
- same physical socket?
- same electrical pin layout in socket?
- are NVLink/OpenCAPI backwards compatible protocols?
that I can’t begin to guess the answer to, but with this many unknowns, and little benefit to doing so, my guess is no.
henriok on Twitter found some interesting info about chip codenames in a recent skiboot patch:
https://lists.ozlabs.org/pipermail/skiboot/2019-February/013193.html
I’ve done a bit of skimming through the skiboot repo (details are collapsed below) but I’ve come across some interesting observations.
- POWER8E is separate from POWER8 NVLink (wiki needs to be updated I guess)
- multiple places in the code order POWER8E before POWER8
- this newer “POWER9P” chip has a codename “Axone”; this is probably to stress IBM’s new PowerAXON naming for the combined A Bus, X Bus, OpenCAPI, and NVLink interface
- while POWER7+ is shortened to P7P in places, I still don’t think P9P is meant to imply POWER9+. cpu-common.c for example treats P9P as just another POWER9 chip, while P7P (POWER7+) is treated as an entirely separate chip from P7
Chip Lists from Specific Files
doc/platforms-and-cpus.rst
Power8E 0x004bxxxx Murano
Power8 0x004dxxxx Venice
Power8NVL 0x004cxxxx Naples
Power9N 0x004e0xxx Nimbus 12 small core
Power9N 0x004e1xxx Nimbus 24 small core
Power9C 0x004e2xxx Cumulus 12 small core
Power9C 0x004e3xxx Cumulus 24 small core
Power9P 0x004fxxxx Axone
external/xscom-utils/sram.c
#define PVR_TYPE_P8E 0x004b /* Murano */
#define PVR_TYPE_P8 0x004d /* Venice */
#define PVR_TYPE_P8NVL 0x004c /* Naples */
#define PVR_TYPE_P9 0x004e
#define PVR_TYPE_P9P 0x004f /* Axone */
asm/head.S
PVR_TYPE_P7
PVR_TYPE_P7P
PVR_TYPE_P8E
PVR_TYPE_P8
PVR_TYPE_P8NVL
PVR_TYPE_P9
PVR_TYPE_P9P
external/xscom-utils/adu_scoms.py
0xf9 P7
0xe8 P7+
0xe9 Centaur
0xea P8
0xef P8E
0xd1 P9 (Nimbus)
0xd3 P8NVL
0xd4 P9 (Cumulus)
hdata/cpu-common.c
POWER7
P7
POWER7+
P7P
POWER8
P8E
P8
P8NVL
POWER9
P9
P9P