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The POWER and PowerPC General Discussion / News Thread



I have found a friend! Well, a few friends. This thread is going to be dedicated to a general continuation of the following thread.

Discussion will include TALOS ][, HPC hardware and news, POWER based workstations, PowerPC projects of both the IBM AND FreeScale variety, Linux and BSD news [as well as other OS’s that may or may not run on these, VM testing, ETC], software listing, and general discussion about the hardware.

Going off topic too far will be stomped. I don’t need another Devilzzz crushout of a thread for fucks sake.

Any concurrent news about the Talos ][ can be found in the above listed thread. I will ask @wolfleben to lock that thread as it is just dragging itself along and I’m sure he’s itching for his fix right about now (srsly see a doctor dude we’re worried about you lol).

At the moment I am working on Java for PowerPC 7445A/A1’s and trying to get a PowerPC 970FX OR MD tower. I’m listing the processors, not the mac’s, because the hardware is what I see as important. I can keep all who are interested updated if they like, but eventually I’ll have an installer for java 6, 7, and possibly 8 for OS X leopard, or at least that is the plan.

In other news, the Talos ][ appears to have some eyes on it from the linux foundation according to Jupiter Broadcasting’s friends in the Discord / Mumble room during one of the last Linux Unplugged’s (either the last one or the time before that one). VERY exciting I think. I can’t wait, personally, to see who snags one. Though, I do wish the Talos ][ would just get released on POWER8. Seems like 9 might be a public chip though so fuck it :U

Edit: Just so he sees the thread: @torpcoms

The TALOS II from Raptor Systems is Interesting
What Would You Like to See From the L1 Forums and Community This Year?

Does anyone know how POWER is generally benchmarked? I know its better for batch processing and analysis tasks, but I always see it compared in HPC with like something at CERN vs SUMMIT or another x86 / ARM processing structure.

I know the intel chips that are in league with POWER can do some neat things, but not everything is 1:1, or at least I would think?


What Torpcoms has been looking at

Talos II news

POWER9 chips, modules

I think I finally figured out what is going on with the different POWER9 processor chips and sockets/modules. There are three chips planned:

PowerNV PowerVM
Scale Out Nimbus ???
Scale Up Cumulus

Nimbus chips - are packaged as Sforza, Monza, or LaGrange modules. They are made with 24 SMT4 cores on the die. Sforza modules are 50 mm × 50 mm, smaller than the Monza and LaGrange modules which are 68,5 mm × 68,5 mm. I don’t know if LaGrange and Monza sockets are physically the same or not.

Cumulus chips - are planned for use in NUMA machines with many sockets. These are made with 12 SMT8 cores on the die, and use centaur-buffered RAM to address much more memory than Nimbus chips. I have seen nothing about what modules will be available.

??? chips - There were plans for Scale Out chips for PowerVM use, but I have seen no mention in the news as to what these chips might be called. These would be SMT8 chips meant for 2-core systems using direct-attached RAM.

Scale Up PowerNV chips (SMT4 with buffered RAM) are a theoretical design possibility, but IBM does not expect to actually make these.

Chips vs Modules

The modules of a chip such as Sforza, Monza, LaGrange, are different packages for the same silicon that expose different IO.

Chip types explained in more detail

There is a matrix you will usually see in POWER9 presentations (and articles using those slides) about chips being made for both the “Linux Ecosystem” or the “PowerVM Ecosystem” and both “Scale Up” or “Scale Out” machines.

Linux Ecosystem Community - as far as I can tell in this context, is synonymous with OpenPOWER; OpenPOWER systems run as PowerNV (not-virtualised) meaning that software runs bare metal, without the PowerVM hypervisor. In my table I use PowerNV for this category; since Linux can run on PowerVM, saying Linux ecosystem is more confusing.

PowerVM Community - refers to systems running software on top of IBM’s PowerVM hypervisor. This is the pre-OpenPOWER way of running software on POWER machines (random history: originally the flag indicating that the hypervisor is running was undocumented, and no one even knew there was a hypervisor in their system).

Scale Up - refers to machines with many sockets. These can be components of systems like IBM’s E880, where an entire cabinet with multiple racks functions as one machine. In the matrix, you will see that there is more SMP connectivity so that all processors (16 sockets is the maximum from what i can tell) can talk to each other.

Scale Out - refers to machines designed for two sockets. These can be stand alone boxes, and have directly attached memory in POWER9, while in POWER8 all machines used Centaur buffered memory.

SMT8 vs SMT4 - Power9 cores are designed out of “execution slices”. Compared to an SMT8 core, an SMT4 core has half the number of these slices. This is why POWER9 chips are either 12 or 24 core, both have the same number of slices. Pairs of SMT4 cores also share cache, since that pair would be a single core on an SMT8 chip.

I have been trying to figure this out for a while, looking through articles from IT Jungle, Next Platform, asking around on reddit’s /r/OpenPOWER, watching presentations on OpenPOWER (I mention some of them in the Talos thread). The POWER9 presentations recorded by the AIX Virtual User Group are especially helpful, though their site is an AJAX monstrosity, so here is a direct link to where the recordings+slides are. I also watch the Raptor Engineering GNU Social account, and sometimes their and Raptor Computing’s Twitter accounts for Talos-specific news. If I know something, you can probably find more detail in one of those places.


Where I think it’ll be most interesting is in the really general-computing category where CISC stuff has well and truly entrenched itself. Things like hardware AES and intel-licensed SIMD extensions. I would like to see an actually open platform in the mainstream, but it needs to be good at things like playing 4K video and games (obviously which are compiled for it)

Hell even Level1’s little baby makes use of SSE.


Where you should start is with the powermac’s. Apple dropped those and 4 years later dropped anything lawsuit related unless you pirated iwork. A 970FX system at 2.5 ghz is fun to play with, but the quad cores are capable of 4k video at 60fps. Last night I got my ibook G4 to run youtube natively without much of a hitch. At that they have OpenFirmware on them rather than a bios or efi so they are basically serversmthat fold or sit at your desk. I’d start studies there since they are available.

Next place you’d want to look is freescale. POWER is nice but its meant for the warking market iw all honesty. PowerPC is still pretty big and the easiest way to get ahold of it is the AmigaONE machines. The next release of chips and the next amigaone are going to be 4 core machines, but they are really fast in their current dual core state.

This is all a lot more accessible than people think lol.


POWER does have its own SIMD and AES instructions. The newer vector instructions are called Vector-Scalar Extension (VSX); but the older instructions are have different names: IBM calls them Vector Media Extensions (VMX); Freescale, AltiVec; and Apple, Velocity Engine. The AES instructions don’t have a fancy name as far as I can tell.

The Power ISA document for version 2.07B barely even mentions VMX, and version 3.0B never mentions VMX at all. So my impression here is that VSX is a superset of the VMX/AltiVec/Velocity-Engine specification. Otherwise, how could you never mention it in the version 3.0B spec?

@Aremis, you were planning on doing some Power assembly, does this sound about right?

Edit: I found a table for Vector support in IBM’s compiler documentation:

Architecture Graphics support Square root support 64-bit support Vector processing support Large page support
pwr4 yes yes yes no yes
pwr5 yes yes yes no yes
pwr5x yes yes yes no yes
ppc yes yes yes no yes
ppc64 yes yes yes no yes
ppc64gr yes yes yes no yes
ppc64grsq yes yes yes no yes
ppc64v yes yes yes VMX yes
ppc970 yes yes yes VMX yes
pwr6 yes yes yes VMX yes
pwr6e yes yes yes VMX yes
pwr7 yes yes yes VMX, VSX yes
pwr8 yes yes yes VMX, VSX yes

Also, a paper on Power SIMD at ResearchGate I am currently reading.


PowerPC assembly, yes. I hawe some utilities I want written for my ibook and I’m not going to jackshit aroutd with C its too slow.


I’ve seen IBM materials advertising simulated transaction tests (video example), some sort of financial benchmarks (article), and an assortment of benchmarks by AnandTech (article). These are all POWER8 benchmarks, and some of them are run on PowerVM systems, some on PowerNV (OpenPOWER).

I need a lot more time to read over these, to be able to tell you something helpful, but here are some links to start.


Quite nice, thanks for the clarification.


Can you message me all the reference material you have so far? I want to start compiling papers and demo material in the first post.


Awesome. I was worried that my explanation was going to make sense to no one but me.

Having three names for a set of instructions is a pain to explain (assuming I even understand it correctly), especially since AltiVec also refers to Freescale’s implementation (but not IBM’s), and an API. IBM chips implement an ISA that you can describe as Altivec/VMX/Velocity Engine, but that hardware is not the AltiVec implementation.

The Wikipedia entry for AltiVec is a mess, but, bless its heart, it’s trying:

The bit about AltiVec also being an implementation and an API?
I’m forgetting where I read that, so take it with a grain of salt


I found this image comparing POWER8 Turismo and POWER9 LaGrange modules in a tweet by Adi Gangidi.

Using the size given on the OpenPOWER portal of 68.5 mm for the LaGrange modules, Turismo is probably about 45 mm. Sforza modules are 50 mm according to the OpenPOWER portal.


I am hard.


Maybe the POWER8 benches from anandtech is interesting, tbh I have no knowledge on POWER but I found the read interesting anyway.


Actually very very helpful. I didn’t know they did benches and I’m soon going to dedicate time to learning the architecture and making a reference doc in the first post like I did with the AMDGPU Info / News thread.


Timothy Pearson on the RCS wiki uploaded a chip diagram showing where the PPE cores are in the POWER9 Nimbus chip:

Technically it doesn’t say this is the Nimbus chip, but the other planned chips are SMT8; as far as I know no other SMT4 chips are planned


Why can’t we have a more interested community


They probably are but they’re just lurking.


Interested definitely, but it’s little more than an interest at present. I would absolutely love to do my computing on a totally open platform, but the pragmatic approach for almost everyone at this stage is to just use Intel’s ISA and keep the lube handy…


Yeah, most people don’t quite have $2000+ spare for a quad core CPU and motherboard. Mark my words though, I’m definitely putting some cash aside for something similar at least.