Forget x86; OpenPower is it! Talos II Secure Workstation! | Level One Techs

[commodore256]

I really wanna see avx512 on power lol

Maybe we’ll see VSX-512 and IBM owing Redhat might turn it Yellow Dog Linux.

[FaunCB]

I’m all in on the vsx I wanna beat the other shit with a lead pipe till it contracts legionnaires

[olddellian]

Liquid Cooling

I mean, IBM already has liquid-cooling blocks for the Monza module sockets on the AC922 systems; as far as I know those might well work on POWER9 Sforza as also.

I was comparing images of the sockets, and it looks like the mounting mechanism might be the same across all currently available POWER8 and POWER9 chips:

olddellian (olddellian)

If you look at the start of that Twitter thread, @q66 was successfully using Raptor’s heatsink (intended for POWER9 Sforza) on a Tyan POWER8 board.

---

512-bit VSX

AFAIK:

• VSX, starting with POWER7, is 128-bit on 64 registers
• AVX2 is 256-bit on 16 registers
• AVX512 is 512-bit on 32 registers

IIRC, Zen’s AVX system was still internally 128-bit wide, but took 2x cycles on 256-bit operations. I think Zen2 is now 256-bit internally.

So, it sounds like VSX on POWER9 should be performing like AVX2 on Zen or Zen+, right? Just with way more registers to work with. Then Zen2 or any other native AVX2 processor will be faster, but have fewer registers.

So AVX-512 would be where POWER9 actually starts to be outmatched in both register capacity and execution speed, right? However, I’ve heard AVX-512 on Intel doesn’t actually run at full clockspeed (due to overheating?), so would a VSX expansion to 256-bit be close enough in performance?

If expanding VSX to 512-bit would require clocking down the whole core, I would guess that IBM wouldn’t even bother; especially with GPGPU, FPGAs, and other accelerators being brought closer to CPU through CAPI/OpenCAPI/NVLink.

This is pretty much the question I was asking in February:

Optimal SIMD/Vector array width

Current State of Vector/SIMD ISA Architecture SIMD width SIMD ISA Intel 64 Skylake-X 512 bit AVX-512 AMD64 Zen 128 bit AVX AMD64 Zen 2 256 bit ? Power POWER9 128 bit VSX ARM Cortex-A8 128 bit NEON According to @Methylzero, AVX on Zen is internally 128 bit wide Question What is the theoretically optimal SIMD width for CPUs? I would guess this varies based on use case, but I’d be curious what people’s thoughts on this are. Considerations Use case (duh, not everything on CPU is SIMD heavy) At some point, moving the data to a GPGPU or ASIC probably becomes more efficent large TDP difference from SISD operation, as on Intel’s AVX-512 CISC/RISC ISA making a difference? Why are you asking about this? Partly based on a February Lounge post by @wendell, in response to me asking about the Talos II board he is testing; maybe the SIMD width of 128 bits on POWER9 is a limitation? But Zen’s SIMD is also 128 bits wide too… and also information I’ve been thinking about from these two threads: in the FMA thread, I asked this question specifically about Power but knowledge on that is a bit more scarce, so I’m curious what information/discussion a more general question will turn up.

Also, some good discussion in the FMA4 thread:

FMA4 on Zen: Forgotten Instruction set, but not yet gone | Level One Techs

256 bit wide vector operations are super useful, and can get you a ton of extra speed. There are diminishing returns in widening the ISA though, especially if the CPU has to stay within a TDP budget. AVX-512 is faster than regular AVX/AVX2, but the CPU has to drop the clock speed to stay within TDP, so the speedup is often modest, and sometimes using AVX-512 can even result in a performance loss, due to the clock speed drop. As for why IBM have not done it, one can only guess.

[commodore256]

I suppose something like that would be easier if IBM were to use Chiplets in Power10, they could bin everything for the enterprise and sell the cheap garbage stuff that they have to downclock to Raptor Computing for their lower end systems for developers or we could get a new PPC Amiga.

[FurryJackman]

Looks like you have a fan.

From: https://pcpartpicker.com/b/9n3bt6

[1ms_hand2eye]

Why is that? Power9 hasn’t been exercised very much, so if its popularity isn’t rising very much, then perhaps it makes more sense to wait for RISC-V… And just live with the PSP/ME backdoors for now.

I’m not sure the connection @wendell was making between openpower & the above security paper - but I’m guessing it is just the fact that whatever can be hidden in the closed architectures of common CPUs. Which yes, I think that can be counted on - considering the funding these companies need and those who have the money to help (and their intentions).

Power10 seems pretty great with the memory encryption features that EPYC / Ryzen PRO has… And who knows how long it will actually take for RISC-V servers are available.