I wonder if one of the Windows settings invoked that message, I know Windows sometimes runs applications in virtualized sandboxes in the name of security.
That makes sense, the UMA settings are for the chiplet based Xeons since chiplet to chiplet communications aren’t as easy as with monolithic.
I was only able to get the hypervisor message to go away after the full combination of settings I posted above. I had actually disabled the memory integrity setting in windows as one of the first things I tried, but it didn’t help. I think the last things I did was disable Extended APIC, and VTd(because it kept getting turned back on unless I disabled Extended APIC).
In the newer build of AIDA is actually puts a little yellow “Hypervisor” text above the Save button, instead of only throwing the error after the test. I see it’s not in your screenshots and you’re actually using a slightly newer build than I am. I wonder if it just isn’t a thing in the stripped version of windows you’re using?
Disable hyperv via bcdedit, and the notification will cease in AIDA:
bcdedit /set hypervisorlaunchtype off
Re-enable hyperv
bcdedit /set hypervisorlaunchtype auto
Apologies if you already know this. Mentioning just in case.
Does this just disable the message, or does it result in ‘metal native’ benchmarking results?
Also, if this allows metal native performance, does this prevent you from using WSL2 and VM functionality that requires DirectIO, etc?
Yes to all.
After disabling Windows hypervisor, reboot. Re-enable, reboot, and WLS2 and VM functionality return to normal. It’s a simple and quick change to make.
Marginal difference in AIDA64 memory test. But there is significant performance increases for both Nvidia and AMD GPU’s with hypervisor off in benchmarks like 3DMark.
For the most part I leave hyperv on since I need it for WSL. I’m certainly not missing the additional framerate when gaming – it’s good enough.
I know I’m late on this but I only just now realized virtual numa and SNC are completely different things. I had assumed virtual numa was another name for SNC since it increased the numa nodes exposed to the OS but that is not the case. Also the W790 SAGE has no SNC settings which contributed to my confusion.
I just learned about this when Supermicro recently added Virtual NUMA and observed the behavior as well. My understanding is that Virtual NUMA splits CPU grouping without breaking Hemisphere/Quadrant memory access, while SNC actually isolates the cores into two or four sub-NUMA.
That is my understanding of Virtual NUMA as well based off of Lenovo’s manuals for their 4th gen scalable servers:
Another thing worth mentioning is that with Virtual NUMA, all PCIe devices will be hanging off the first Virtual NUMA group, while SNC on 4th Gen will have PCIe hanging off each corresponding tile(s).
(This is Virtual NUMA, I can’t have SNC lstopo right now since it’s running a workload)
So I contacted ASRock about the VT-d setting in the BIOS not working, and they sent me a test BIOS, and while the setting no longer reverted upon reboot, I could no longer boot to Windows, getting stuck on the “Preparing Automatic Repair” screen. Re-enabled the virtualization options and ran sfc /scannow as it corrupted some files.
Reported this back to ASRock and they sent me another BIOS. Got the same result. Told me to clear CMOS, same result. At this point I said I was fine with leaving it on but to fix some of the other things I requested (MB+CPU temp monitoring, fan hysteresis, “PH Randomization” defaulting to enabled even though it specifically says “DO NOT ENABLE ON PRODUCTION PLATFORMS”). They didn’t fix any of these things in the BIOSs they sent me, and I haven’t heard anything back since.
Hi, new here. Building a system on w790. Almost all components bought already , and now looking for a memory. Local store have following modules available:
Memory modules will be used with ASUS W790E-SAGE and W5-3435X processor
Thanks
If my memory of what buildzoid said is correct, the x8 organized RAM is supposed to be best for overclocking because it tends to have more consistent trace lengths to the DRAM ICs as compared to x4 organized DIMMs. That would narrow the choices down to either #1 or #2.
I’m assuming W790 benefits in performance from dual rank memory over single even if you can’t hit as high of a frequency on dual rank so that would narrow down the choice to #2.
Looks like the W-3500 series isn’t going to be Emerald Rapids, kind of disappointing:
The ~300% increase in LLC would have been really nice.
Seems like there must be a half step or something… Since we know the number of cores they’re fitting on a tile has increased significantly for the MCC chips. they’re getting more total cores out of 2 tiles compared to 4 tiles of the 3400 series.
It seems like its just Sapphire Rapids again with presumably better bins from an even more mature process.
Same exact 1 MCC die for the W2500 and same 4 tiles for the XCC W3500 processors.
The MCC die hasn’t even changed for full on Emerald Rapids, its still capped at 32 active cores as it was for Sapphire Rapids.
Maybe I’m blind but I don’t see where that says the tile count for XCC remains unchanged at 4? The Der8auer video where he had a chip in hand showed two tiles and he mentioned this was an upcoming refresh chip: youtu(dot)be/VQV-72D6hTM?t=417 Linked to appropriate timestamp. Sorry I’m still too noob to embed links so I had to butcher the url a bit.
Also note, the image in the first article you posted shows two tiles.
It doesn’t explicitly say the tile count for the W3500 XCC Xeon W’s will be 4, but considering the amount of cache that they have on board and the fact that they can still service 112 PCIe lanes, they must be the 4 tile XCC dies as opposed to the 2 die XCC processors that Emerald Rapids brings (Emerald Rapid’s 2 tile XCC architecture can only address 80 PCIe lanes and has triple the amount of cache).
I find it confusing what the word “Refresh” means in this context, it seems like when some people (Der8auer) say refresh they mean the next generation/architecture of processors that fit on a given socket/platform, while others mean just a better bin or new stepping of an existing processor (like raptor lake refresh/14th gen).
It it entirely possible I’m wrong on this, but it seems like this is the case given the available information.
It’s also not completely surprising that Intel kept producing Sapphire Rapids XCC processors even when Emerald Rapids is out, we knew for certain that there were going to be no HBM variants of Emerald Rapids and that Intel was going to continue producing and selling HBM Sapphire Rapids.
Edit:
Sapphire Rapids MCC= 1 tile
Sapphire Rapids XCC= 4 tiles
Emerald Rapids MCC=1 tile
Emerald Rapids XCC= 2 tiles
This makes me have hopium that there will be SR, SR Refresh, ER, ER Refresh for our socket… Don’t play with my heart, intel!
Good aftermorning!
I wasted money on some 6800 memory & tuned it to 7000MTs 32-40-40-80 hoping to get a bit more performance from it, only to get roughly zero improvement so that was… fun… but the upside is at least this set doesn’t totally suck when trying to increase frequency like the 6000 set did, another user mentioned an early RCD chip as the cause of that…?
Anyway, has anybody attempted to increase the Mesh frequency at all? on the SAGE motherboard with a W3400 chip, it looks like its capped at 27 and I’m not certain if its a hard limit or another BIOS limitation like the 5.2GHz frequency cap was previously, as if its not a hard limit, I might try my luck asking ASUS if they could change that setting in a future BIOS release.
Not holding my breath for a Emerald Rapids launch instead of SPR refresh so hoping to get the absolute most of this one )
I’ve found that the aida64 memory write speed seems bottlenecked by the mesh speed fairly strongly.
I’m running a 2.835GHz mesh frequency and saw basically linear increases in write speed as I brought the frequency up. I had to use the BCLK to up my mesh frequency past 2700MHz which is non ideal because of how hard BCLK OC’ing is.
Unfortunately the XCC (W3400) series Xeons have a x27 mesh frequency multiplier limit which makes mesh overclock more difficult compared to the MCC Xeons which have a x80 mesh frequency multiplier limit; this is something that’s baked into the processors as opposed to the motherboards.
wait, what? I think I missed this one; although it was pretty hard to get above 5.2GHz simply because of silicon quality.
It’s probably not a bad idea to ask anyways, maybe there is something ASUS can do to circumvent that x27 multiplier limit. heck if the refreshed SPR processors came with higher mesh limits that might be worth it along because the mesh seems to be the bottleneck for alot of memory operations.
