Thought experiment: Making SLC SSD from MLC, TLC or QLC drive

Hardware HDD's & SSD's
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Why? Purely for science. That and I cling to the conspiracy theory that SLC is vastly superior for using NAND as cold storage.

I had an epiphany when I first read about dynamic SLC cache for SSD’s: the NAND doesn’t determine the bit depth, the controller does, and this can be changed.

So the question is, is there a way for a user to change the bit-depth on any consumer drives, whether officially supported, or through hackery?

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It sounds like it is perfectly reasonable theoretically.

Here is a drive that is like that-
https://www.anandtech.com/show/15530/memxpro-introduces-pc32-full-drive-slc-ssds

Although the write endurance is not as much better as I would have expected, so I guess there is a reason that it is pseudo-SLC not SLC. If you manage to dig up more information, this could be a very interesting topic.

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Where I would start is looking up your specific ssd controller and learning ewerything you can about it. What chipset is it based on, what is the pinout, can it be flashed, etc. Either you can, most likely, reflash the controller, or solder on a different one. The latter option is… difficult.

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Personally, I’m well past the point of being concerned about write endurance, even QLC far exceeds what I could reasonably write to a drive over an expected lifetime, even accounting for logfile spamming.

Though even after reading the article I’m confused as to what pseudo SLC means?

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Interesting, especially in light of @wendell’s recent Talking Storage with Allyn Malventano video, I wonder if you could use MLC storing only single bits per cell to even further reduce wear on the NAND.

Dynamic MLC Degradation - personal theorising

Imagine a 3-bit MLC (TLC) cell, where the levels simply map to bits in this way:

Level L0 L1 L2 L3 L4 L5 L6 L7
Bit values 0-0-0 0-0-1 0-1-0 0-1-1 1-0-0 1-0-1 1-1-0 1-1-1

Since it sounds like you can only increase the level or reflash to L0, I imagine in many cases, to flip any one of the 3 stored bits, you would need to reflash the entire cell.

If you instead were to store only 1 bit, but still make use of all eight levels:

Level L0 L1 L2 L3 L4 L5 L6 L7
Bit value 0 1 0 1 0 1 0 1

Theoretically this could let you toggle an individual bit up to 7 times before needing to reflash the cell. Then as the cell eventually degrades and hitting the discrete levels becomes less acheivable, you could dynamically convert to emulate a 2-bit MLC mode:

Level L0 L1 L2 L3 L4 L5 L6 L7
Bit value 0 0 1 1 0 0 1 1

or eventually SLC, with further degradation:

Level L0 L1 L2 L3 L4 L5 L6 L7
Bit value 0 0 0 0 1 1 1 1

To my mind, this seems like it could potentially achieve better endurance than even SLC alone, as the reflashing events would be substantially reduced. Thoughts?

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Iirc, and I could very well be wrong, but a cell/page/word is marked by an SSD’s firm ware/controller as bad when it no longer reads a reliable, or accurate voltage from it.
The idea being the P/E cycles are slightly destructive, and the cells break down.
With an SLC, the drive only needs to have X charge stored, and if a cell does not hold it, it gets marked as bad.
Deeper levels require differing voltages, so perhaps a QLC drive would hold up well, even though the quality might be a bit less, and the chips are much more dense, and being a smaller lith, there is less actual material, But as the cell was going to store a wide range of voltages, the sensor might be more accurate, and the cell might not have to store As high a charge/voltage to register as a 1, or 0 and so might benefit from that as well?

So I posit, and am happy to be told I’m wrong, but IF the read sensor is more accurate, And the cell requires less charge to set, the the chip, and hence drive, would probably be cheaper than an SLC with similar capacity, and last a similar time? Even though new QLC chips might be a lot less durable.

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Ah, so to adapt that to 3-bit MLC (TLC) model, you are thinking of:

Level L0 L1 L2 L3 L4 L5 L6 L7
Bit value 0 1 N/A N/A N/A N/A N/A N/A

where we never add more than L1 worth of charge, and hope that reduces wear on the insulator?

That is an interesting thought. I really do need to read more in depth about NAND, I really am just speculating for the fun of it, and have little idea of how realistic either of our ideas are.

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I have no idea, and electrical stuff probably doesn’t work that way. The capacity at the end could work out worse in fake SLC drives than just getting a native one anyway.
Added to the trickyness of the firmware update, it’s all an unknown.

Nice thought experiment though, thanks

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