Condor is going to be an ATX sized single-socket LaGrange board, with the main benefit being LaGrange’s OpenCAPI/NVLink lanes. A quick bullet-list of information:
Well with the current COVID-19 disaster in full swing and supply chains crippled, Condor will likely be severely delayed. In which case… I might as well wait for POWER10 to finally drop in around 2021, as that platform is rumored to support DDR5, PCIe 5, offer a 7nm feature size on transistors, and a possible bump up in SIMD instruction width, at around 256-bit or perhaps even 512-bit, which would be a massive step up from the AltiVec era 128-bit SIMD of POWER9.
Suffice it to say, POWER10 should be ridiculously future-proofed for me.
as i sit ordering small pcb’s, ram, and clothes from china and they arrive no slower then before covid-19 showed up only thing from china that i’ve heard of being slowed down is deepin v20 which deepin being based in wuhan its a bit more stalled then most regions.
all in all this panic on covid19 is laughable unless it gets way more lethal or spreads faster
that being said i can order custom pcb’s and they show up 2 weeks from now like always
A smart man (winkwink) said recently that these sort of pandemics have a selection bias to appear more deadly because a lot of the mild cases go uncounted until the wave is over and doctors can start running antibody tests on the general population.
Basically, this idea that it’s 5% is about as logical as not believing in the moon landing.
Believing 2% is probably high as well. I’m thinking 0.5% will be the final toll.
As a quasi-segway to keep this thread on topic, the two fanciest POWER9 supercomputers (Summit & Sierra) are both getting tasked to work on protein-solving for SARS-CoV-2/COVID-19:
Sierra getting utilized is especially notable, since it is meant for nuclear stockpile management, and therefore unlike Summit is usually not available for academic research.
It connects to each of the systems individually and runs checks like weekly or some crazy shit like that. Its part of the automation program for the governments redo of the silo’s. It also does compute stuff in its off time, so doing things like this. But its not always available.
Simulations of the weapons to ensure long-term-stability/effectiveness is the rough understanding I have. I have also seen it mentioned as the natural result of nuclear test banning; so maybe nuclear weapon research as well?
Here is some of the official writing about Sierra, ASC, and NNSA:
[Sierra] provides computational resources that are essential for nuclear weapon scientists to fulfill the National Nuclear Security Administration’s stockpile stewardship mission through simulation in lieu of underground testing. Advanced Simulation and Computing (ASC) Program scientists and engineers use Sierra to assess the performance of nuclear weapon systems as well as nuclear weapon science and engineering calculations. These calculations are necessary to understand key issues of physics, the knowledge of which later makes its way into the integrated design codes. This work on Sierra has important implications for other global and national challenges such as nonproliferation and counterterrorism.
Because the United States also voluntarily ended underground nuclear explosive testing, NNSA uses a science-based assessment of the reliability of nuclear weapons to assess and certify the stockpile without nuclear explosive testing, called the Stockpile Stewardship Program.
…
NNSA scientists are able to accurately model nuclear weapons performance and physics without nuclear explosive testing. To accomplish this, NNSA conducts new scientific research and combines it with existing data from past nuclear tests, the nation’s long history in nuclear science, and computer simulations.
…
NNSA delivers leading-edge computer platforms, sophisticated physics and engineering codes, and uniquely qualified staff to support addressing a wide variety of stockpile issues for design, physics certification, engineering qualification, and production.
I don’t have proof besides me calling into Raptor support and asking about it. They mentioned they had supply chain delays, and I figured that was as a result of COVID. I mean it’s great news that the flow of goods are mostly back to normal, but I’d imagine that more niche operations like Raptor’s would still be delayed anyway.
Perhaps my language was somewhat hyperbolic in retrospect. That wasn’t the intention.
It’s all good, I could have been overly critical too. I’ve been putting up with people (idiots) at my company losing their heads running around like it’s got a 90% death rate and every time I see “because covid” I have an autonomous response to reee.
I won’t be surprised if things are delayed, that’s what happens when you work on a small volume project with China. Additionally, there are small delays being caused by covid. It’s not like the “we’ll run out of components by April” that organizations like LTT are claiming, but it’s definitely a slight delay.
You are absolutely spot on about the hysteria around COVID. If people take reasonable precautions as they would during a normal flu season, this would almost be background noise in the grand scheme of things. But alas, somebody has to profit off the panic.
So I attended the recent OpenPOWER coffee chat session hosted by Hugh Blemings. Seems like this will be done a few more times at least, and if anyone wants to check this out, here’s the link.
Slightly off topic note, but I recently went looking through the ATX and SSI EEB specifications, trying to understand the standoff layout on the Talos II, which is marketed as EATX. This was largely prompted by Gamers Nexus’ article about EATX being undefined (or video if you prefer), as Raptor’s website and even wiki makes no mention of the SSI EEB specification that mostly describes the form factor that Talos II actually uses.
I started a thread about this on the RCS forums if you want more details, but it seems like Talos II is using SSI EEB-compliant mounting locations (some of which are alternatives to the ATX locations), but then replaces the use of an EEB-required location C with a mounting location that not used by SSI EEB or ATX.
This mounting location is labelled B in the microATX specification, but if you were using SSI EEB conventions it would probably be called C′. I think this might date back to the IBM AT board, but I cannot find a specification for that.
Regardless, it makes for an interesting situation where you probably need a chassis/case that is both microATX and SSI EEB compliant to have all the necessary standoff holes predrilled.
The issue is that they do not mean SSI EEB, since their B (or perhaps C′ if you prefer) mounting location is only compliant with versions of SSI EEB older than 3.5; a modern chassis that is SSI EEB compliant is not guaranteed to have that mounting location.
SSI EEB v3.51 is copyright 2003, so this B/C′ hole has probably been obsolete for at least 16 years.
Apart from being inherently awesome due to the “we do it because we can” factor; what is the goal of this port?
What does André plan to test against?
Were it for Big-Endian Power, I would assume your first test case could be applications from the old Windows NT port to PowerPC.
You could strap this to QEMU and perhaps run x86 Windows applications that way; I think Darwine was working on this in the Macintosh PowerPC era
some other usage I am not imagining?
I was expecting to see a Darling port before Wine, but I suppose stranger still is the choice to port to Little-Endian first; but maybe too much has changed in winelib to make Darwine’s work usable?
