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The POWER and PowerPC General Discussion / News Thread

Roadmap to POWER10

I keep seeing similar looking roadmap charts with minor changes between them, so I thought I would make a post here with what I find as most recent info:

General Availability 2017 2018 2019 2021+
Cores 12/24 12/24 12/24 TBA
Lithography Globalfoundries 14nm Globalfoundries 14nm Globalfoundries 14nm Samsung 7nm
Marketing New Micro-Architecture

Direct Attach Memory

New Process Technology
Enhanced Micro-Architecture

Buffered Memory
Enhanced Micro-Architecture

New Memory Subsystem
New Micro-Architecture

New Technology
Sustained memory bandwidth 150 GB/s 210 GB/s 400 GB/s 435+ GB/s
Standard I/O Interconnect PCIe Gen4 x48 PCIe Gen4 x48 PCIe Gen4 x48 PCIe Gen5
Advanced I/O Signaling 25 GT/s
300 GB/s
25 GT/s
300 GB/s
25 GT/s
300 GB/s
32 & 50 GT/s
Advanced I/O Architecture CAPI 2.0,
OpenCAPI 3.0,
NVLink 2.0
CAPI 2.0,
OpenCAPI 3.0,
NVLink 2.0
CAPI 2.0,
OpenCAPI 4.0,
NVLink 3.0

I’m mainly using the 2018 October EU OpenPOWER Summit OpenCAPI presentation as a reference, but also adding info from a Jeff Stuechelli video saying 400 GB/s per socket, and POWER10 as “some time after 2020”.

IBM terminology

The suffixes used for revisions of POWER chips have specific meanings:

Plus sign +

a “plus” chip in the IBM lingo means something very precise, and that is usually a process shrink coupled with some slight microarchitecture changes

from NextPlatform article on new roadmap (April 2016)

Prime symbol ’

it designates a change in the I/O and possibly memory subsystems in a Power processor; it is distinct from a plus sign, which means a change in process or architecture or both in a Power chip, but well short of a major version which has big changes

from Nextplatform article on Samsung as POWER10 fab (December 2018)

Sources and past roadmaps

Because the OpenPOWER machines only use SMT4 chips, some roadmap charts intended for OpenPOWER audiences may say “24 cores” rather than “12/24 cores”.

However, it is entirely possible for OpenPOWER vendors to use the SMT8 chips, though they choose not to:

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Hmm… I wonder if that POWER9’ chip coming out this year in 2019 will be drop in compatible with existing boards? Am I reading your chart correctly @olddellian?

I am almost certain that no, it will not be. The main point of buying one of these would be to use OpenCAPI 4.0 or NVLink 3.0, which would probably need a board redesign anyway.

NextPlatform wrote last year about POWER9’ potentially using OpenCAPI to interface with OpenCAPI memory as an alternative to POWER9 SU using SerDes to talk with Centaur-buffered memory; this is potentially further incompatibility with POWER9 SO&SU boards. You can read about OpenCAPI memory here:

Though I don’t really know all that much about these sockets. I never did get a reply about whether SO (Scale Out) and SU (Scale Up), even use the same physical sockets.


From the RCS Wiki talk page on POWER8’ (listed there as POWER8E):

We have no direct experience with this module, aside from the fact that it does not work (or even fit) in the standard POWER8 socket.

Though that’s not a fair comparison, since POWER8 → POWER8’ added NVLink connections, whereas POWER9 → POWER9’ is only updating them.


There are a bunch of questions here,

  • same physical socket?
  • same electrical pin layout in socket?
  • are NVLink/OpenCAPI backwards compatible protocols?

that I can’t begin to guess the answer to, but with this many unknowns, and little benefit to doing so, my guess is no.

henriok on Twitter found some interesting info about chip codenames in a recent skiboot patch:

I’ve done a bit of skimming through the skiboot repo (details are collapsed below) but I’ve come across some interesting observations.

  1. POWER8E is separate from POWER8 NVLink (wiki needs to be updated I guess)
  2. multiple places in the code order POWER8E before POWER8
  3. this newer “POWER9P” chip has a codename “Axone”; this is probably to stress IBM’s new PowerAXON naming for the combined A Bus, X Bus, OpenCAPI, and NVLink interface
  4. while POWER7+ is shortened to P7P in places, I still don’t think P9P is meant to imply POWER9+. cpu-common.c for example treats P9P as just another POWER9 chip, while P7P (POWER7+) is treated as an entirely separate chip from P7
Chip Lists from Specific Files


Power8E   0x004bxxxx Murano
Power8    0x004dxxxx Venice
Power8NVL 0x004cxxxx Naples
Power9N   0x004e0xxx Nimbus 12 small core
Power9N   0x004e1xxx Nimbus 24 small core
Power9C   0x004e2xxx Cumulus 12 small core
Power9C   0x004e3xxx Cumulus 24 small core
Power9P   0x004fxxxx Axone


#define PVR_TYPE_P8E    0x004b /* Murano */
#define PVR_TYPE_P8     0x004d /* Venice */
#define PVR_TYPE_P8NVL  0x004c /* Naples */
#define PVR_TYPE_P9     0x004e
#define PVR_TYPE_P9P    0x004f /* Axone */




0xf9 P7
0xe8 P7+
0xe9 Centaur
0xea P8
0xef P8E
0xd1 P9 (Nimbus)
0xd3 P8NVL 
0xd4 P9 (Cumulus)



New firmware for the talos ii is much more friendly. I gotta get that vid out


Adding some of henriok’s speculation, I think I can summarize what we know:

Variable name Codename Cores Modules
POWER8 Venice 12 × SMT8 Turismo SCM
POWER8E Murano 6 × SMT8 Stradale DCM
POWER8NVL Naples 12 × SMT8 ?
POWER9N Nimbus 12 × SMT8
24 × SMT4
Sforza SCM
Monza SCM
LaGrange SCM
POWER9C Cumulus 12 × SMT8
24 × SMT4
Sforza SCM
Monza SCM
LaGrange SCM
POWER9P Axone 12 × SMT8
24 × SMT4

SMT_ is how many threads per core
SCM is Single Chip Module
DCM is Dual Chip Module

To be clear though, I’m not entirely sure about:

  • Naples being SCM, though I think I read this somewhere
  • Cumulus modules being the same as Nimbus, though I am confident SMT4 vs SMT8 does not affect module name
  • Axone being optionally 12c or 24c, though if it’s a minor modification from Cumulus/Nimbus, I can’t image it not sharing the same properties

It is interesting that the skiboot code/documentation groups SMT4 and SMT8 together like this, I assume this means that SMT4 vs SMT8 really is just the same silicon. I wonder if it is possible to turn a SMT4 chip into SMT8 or vice versa…

Raptor-specific News

Looks like that single socket LaGrange mainboard they mentioned on Twitter last year is coming along nicely; they mentioned it unprompted in a recent tweet:

EDIT: Wendell posted it in its own thread finally :slight_smile:


Dank as fuck.

@wendell is there aaaaany chance that I could be alloweb to remote into yours and play with it? Please techno senpai?


“Power Architecture” and Wikipedia

Apparently earlier this year, Wikipedia editors decided to restructure a bunch of the Power-related articles to remove references to “Power Architecture”:

I’m not sure what to make of that, is it really so different from how we refer to x86-64 and x86 (or more precisely, “IA-32”) as x86, or all the different variantions of ARM as ARM architecture?

Personally I’m just annoyed that all the specsheets for tme ppc machines are wrong on the site. Some of the models are mixed up, a lot of the listed processors are wrong or missing, entire versions of machines gone, no mention of the cost and price difference of the emac and how they had sold 3 versions of the same machine at the same time…

brb I’m too amped about a shit website xD

New post over at Talospace:

Some highlights

the OzLabs developers like the T2 so much they’re ordering more as workstations

He mentions the mapping between some prototype names and the final products they became:
Romulus → Talos II
Witherspoon → AC922
Palmetto → Tyan GN70-BP010
Stratton → S821LC
Briggs → S822

And we finally have a picture of all three modules next to each other:


Blackbird board GA scheduled for May 22nd

The users guide has also been uploaded to the wiki:


Oh, that’s real soon! Nice. I’ve been lusting over the pre-order…

Void Linux on the Wii :slight_smile:

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(I kinda wanted to try that actually lol)

I now have to annoy foxlet for images of what comes up in hardware listings lol

Power9 Blackbird motherboard has just reached General Availability!


Fienix is dropping a proper G5 compatible ISO soon that will actually boot.

I’m ecstatic.

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@stenstorp can it be talked about yet

Presentation about building of the two US POWER9 supercomputers, Summit & Sierra. at Linux Conf AU 2019:

I don’t think I have posted this before, but sorry if I have

New codenames discovered:
Boston → LC922

Notes about Stepping (at 13:45)

DD1 was for prototyping, DD2 for customer release

6 months between major steppings, with 2 months of that spent waiting after submitting design to fab.

DD1 - received 2017 January

Partly proprietary firmware

For Summit/Sierra:

  • Infrastructure nodes (LC922) use proprietary Supermicro BMC firmware
  • Compute nodes (AC922) use OpenBMC