To me, a mobile - or at least mobile-targeted - SoC offering more (theoretical) memory bandwidth if not compute than even same-generation HEDT parts is already not quite the natural state of affairs. If the next generation would push it even further, I’d be more interested to see what they’d do with their next desktop platform. An electrically 256-bit + ECC + 40-lane PCIe socket shared by parts offering 128- or 256-bit memory bus width, with or without ECC, and 12-40 PCIe lanes, seemed not impossible. Even more interesting might be what they do with the 64GB/chiplet bandwidth bottleneck, if just to make that 384-bit interface more worthwhile beyond graphics and iGPU compute.
Right now though, if you don’t actually have $2k burning a hole in your pocket or the room & goodwill for a decommissioned server just to deploy these humongous open-weight models locally for whatever purpose, I think cramming an existing DDR5 desktop setup with as much memory as would fit might be the better value proposition, even if you would then also pay for that in memory bandwidth where DDR5-4800 is apparently already a small win in silicon lottery terms. 
And - disregarding that the 5090 is “cheap” when compared to the PRO 6000 - until there is a “cheap” Blackwell GPU with at least 24GB of VRAM, there’s not much it might offer over the previous generation offerings in terms of fitting the shared layers without damaging model capabilities and with useful context length, at least right now.