[Rumor] AMD reportedly set to launch EPYC 4004 series for AM5 socket

Did you guys see this rumour/leak,

EPYC 4004 using AM5

If true it would be amazing, imagine if they reworked the current Ryzen 7000s io-die so it could allow for 32-48 PCI-E lanes, or you can use ECC R-DIMM for up to 1TB RAM (via 256GB x 4) or they allowed 8 DIMM 4-Channel memory configurations, or give us 8+16 (Zen4 +Zen 4c) or 32 Zen 4c CPUs and hopefully it still keeps its iGPU for transcoding

Also i wonder if that ASUS X690E Pro WS motherboard leak from a month ago is related

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Not going to happen. There’s no way to get more PCIe lanes from AM5, except for io-die you’d also need a new socket and new motherboards (currently AM5 socket has pins for 28 PCIe lanes, no more) so… a TR or SP platform anyway ¯\_(ツ)_/¯

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What if they upgraded the Chipset link to PCIe 5.0 instead of 4.0 and added an additional Chipset to break out the lanes

In this interview with a former AMD senior product manager, around 25:50

He says getting more PCIe lanes in a motherboard is possible with the current Ryzen chips, but the need has to be driven by the market

Even if you had a motherboard with 3 x8 slots or 1 x16 x8 and x4, (all PCIe 4.0) that would be a enough for most

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That is tangental to whether the processor would be a Ryzen or an Epyc. You can’t get more than 28 lanes through the AM5 socket, period. You can get infinite lanes by daisy-chaining B650 chipsets today, it’s just that the latency is worse with each chained chipsets + they share the same 4-lane bus to the CPU. So yes, it’s technically possible to make better motherboards, you don’t need Epyc CPUs to do that.

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Ya, the AM5 socket only has 10 reserve pins available so they could add at most like 2 more pcie lanes? Doubt AMD would go through the trouble, and some of those pins might be used for some new function on the Epyc specific CPU to be released.

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IF they were to entertain, such an amped AM5 chip
…Likely would only work, with “some” stipulation(s) applied
[ex. say X670E boards + firmware → open up full 2 x16 lane slots, when being used]

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some more developments

This is a very interesting packaging play from AMD.

Many of us have complained since the initial release about what is seen as limitations to the current AM5 Ryzen hw:

  • no clear commitment to ECC memory (technically possible on AM5, but inconsistent and badly documented implementation in motherboards)
  • 2 memory channels (sufficient for desktop use, insufficient for workstation-like use cases trying to take advantage of ample CPU power offered by Ryzen CPUs)
  • 24/28 PCIe lane limit (again sufficient for desktop gaming, insufficient for workstation use cases)

Well, AMD then released the Threadripper 7000 lines offering solutions at significant raised price points.

Meanwhile, the EPYC line has run largely parallel and unharmed by this discussion. AMD for a long time could not produce fast enough to meet demand and could sell with a healthy profit margin.

I assume that at this stage demand, especially on the low-end skus, has waned and they’re facing the decision to lower prices to keep moving products.
Arguably, there are many servers to be built and sold that don’t need 64-128 cores, 128 PCIe lanes, 12 memory channels.

Adding an EPYC line of CPUs on the AM5 socket allows creating a lower price point for entry level servers limited by the capabilities of the AM5 socket (memory bandwidth/slots, 16 cores ). By releasing on the AM5 socket they can keep the prices on the existing EPYC products up demanding premium prices from customers committed to that platform.

I would assume the release will introduce

  • a new AGESA that officially disables ECC for Ryzen CPUs (settling that discussion)
  • a new chipset focused on entry-level server market

Maybe we’ll start seeing increased competition with the Xeon-D and Atom lines of Intel servers.

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This does make some sense, Intel has had the entry level xeons for along time; they even just released the e-2400 series. It makes sense for AMD to launch a line to compete with them.

!!!
This would earn them a lot of bad will in the community… but doesn’t seem too far fetched since it wasn’t an advertised feature by AMD themselves.
Also not unprecedented since AMD has release AGESAs in the past that break ECC for their consumer line.

This is what I’d be excited about; AMD has basically been using the same promontory chipset (with a few tweaks) for everything since the 300 series boards, the only exception to this was the x570 chipset which truly was unique and modern-ish.

From a packaging perspective AMD will have to differentiate and defend the EPYC line from the Ryzen consumer line (and the price difference that I would expect to exist between these two).

I hope they figured out and fixed the challenges running with 4 memory slots populated and support dual channel, 4 slots at modern DDR5 speeds (may I hope for 6400MTs?) up to 192GB capacity.

Now the real question is why they picked the AM5 socket as target for this new EPYC line. They have just introduced the TR5 socket with 4/8 channel memory support. Maybe this was too close to SP5 as that socket also support 128 lanes of PCIe?

Maybe it’s a response to Intel’s W680 Chipset, which allowed for most 12/13/14th Gen CPUs to have solid ECC support (just not RDIMMs), or maybe AMD is putting this out because they think/know Intel is going to bring back HEDT in a unique way(whenever Arrow lake comes out), and by AMD doing it first, they’ll have first dibs and AMD can easily update it to Zen 5 variants

So i guess the question is, if this rumor is true, when will AMD release it? Just before Zen 5 (Ryzen) announcement at computex in June or it’ll be a ‘one more thing’ when they announce Zen 5 EPYC (i dunno when that’ll be, but I’m assuming after computex), which then doesn’t make sense because it’ll be CPUs using an older generation

I am sure that it has something to do with that. We will have to see the official announcement to better understand AMDs positioning.

At this point the AM5 platform is limited in its usability. E.g. I wouldn’t touch it for any app that needs more than two sticks of RAM.
However, AM5 is meant to stick around for longer - to do that AMD will have to find ways to keep that socket relevant.

The TR5 platform is very interesting for HEDT, but maybe too pricy.

However, if AMD were to release anything to compete in the HEDT space, they would do that under the “Threadripper” brand. The “EPYC” brand is reserved for their server / data center product line.

Now we’re talking. This extension of the EPYC line could be the item that spices up the release of Zen5.
What else will they be talking about?
faster (yadayada)?
more efficient (yadayada)?

Entering new markets is probably more exiting.

I can imagine that a lot of customers would be very interested in competition in some markets that are currently very dominated by Intel.

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Yeah that’s true, i think AMD is in a weird position where if they released 12 or 16 core threadripper and it had better ST performance than the 24/32 versions(and therefore close to 7900X & 7950X), it would cannibalise the sales of the 24/32 core (and entry level EPYC) since alot of software favours ST more than MT or GPU hardware acceleration or AICs are more desirable than more cores (and they get more PCIe lanes with the platform).

it’s also annoying TRX50 only has 4 RAM slots, instead of 8 (still with 4 channels) because single sticks of RAM higher than 64GB get exponentially more expensive.

It’s a double edged sword when AM5 commits to so many generations, doesn’t it make sense to have a separate socket for EPYC 4004 so they can rework the pins and io die, but that’s probably too much work, i really hope Intel comes back with bangers because AMD’s platform costs for anything other than consumer is pretty high, and most people just want more RAM and more PCIe lanes(but also don’t need >48) and it doesn’t even have to be 5.0 lanes either, 4.0 is still plenty bandwidth),

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True.
Is this a technical limitation? Or rather a branding/licensing/packaging?
The socket is clearly 8 channel capable. The memory controller is embedded in the CPU. So, is SDC vs DDC a limitation in the CPU (as a way to distinct from EPYC) or just the current situation because mobo manufacturers want to see if there is a market for them?

I’m 90% sure it’s artificial segmentation most likely by AMD (and not so much the motherboard companies), because then WRX90 would only make sense if actually need 64/96 cores and full 128 PCIE lanes(in which most actually don’t need or you can’t use all 7 slots with dual slot cards for example), where was if TRX50 had 8 sticks, and you only wanted a 24 core cpu, the hedt version is 1500$ and the pro version is 2500$, there wouldn’t be much reason to get the pro version unless you needed the specific pro features or wanted the full 8 channel memory bandwidth

Plus there’s plenty of EPYC motherboards that for example have 6 channel memory, but have 6 or 12 RAM slots, or Genoa which has 12 channels, but some motherboards have 8 Slots or 12 or 24.

For cheaper multiple memory channels and PCIe lanes they already have Milan extended to 2026: AMD's EPYC 7003 "Milan" Receives Extended Lifecycle: Availability To 2026 With 6 New SKUs

What’s this, a Ryzen but with limited TDP without a note “liquid cooling recommended”, and with guaranteed ECC?

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An AM5 Epyc is definitely intriguing. I’ve been having the itch to finally build a home server, but am in the process of deciding on a case.

Currently have a Meshify 2 being used for my current build, which would work well for a server. It’s pretty much finding something to swap my current build in with a 5900x/X570s. There’s an old OG NZXT Phantom lying around, but have mixed feelings about using it for this project.

I’m waiting until AMD announces the next lineup of AM5 CPU’s to make a decision with what to do down the line.

For the moment there’s an 1800x/x370 (which has a U.2 port, the x570 doesn’t) lying around that could be used temporarily.