PCI 3.0x16 vs. PCI 2.0x16, what do you lose?

I'm just wondering what are the big differences here? Is it detrimental to go with PCI 2.0x16 or are the differences inconsequential?


I was researching some of the next gen AMD motherboards and from what I gather, neither their Trinity or FX Piledriver boards will support PCI 3.0. I'm trying to understand why their motherboards wont support it when their GPUs use PCI 3.0.


Sorry if I'm showing off my noobery, just trying to learn more about computers.

PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. This means a 32-lane PCIe connector (×32) can support throughput up to 16 GB/s aggregate.

PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 will work with the other being v1.1 or v1.0a.

The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.

Intel's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (AbitAsusGigabyte) as of October 21, 2007.AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72.[21] All of Intel's prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.[22]

Like 1.x, PCIe 2.0 uses an 8b/10b encoding scheme, therefore delivering an effective 4 Gbit/s max transfer rate from its 5 GT/s raw data rate.




PCI Express 3.0

PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second (GT/s), and that it would be backward compatible with existing PCIe implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until 2011. New features for the PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization,PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.

Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.

PCIe 3.0 removes the requirement 2.0 has for 8b/10b encoding, and instead uses a technique called "scrambling" that applies a known binary polynomial to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial. and also uses a 128b/130b encoding scheme, reducing the overhead to approximately 1.5% ((130-128)/130), as opposed to the 20% overhead of 8b/10b encoding used by PCIe 2.0. PCIe 3.0's 8 GT/s bit rate effectively delivers double PCIe 2.0 bandwidth. PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.

On November 18, 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.

AMD latest flagship graphic card, the Radeon 7970, launched on January 9, 2012, is the world's first PCIe 3.0 graphic card. Initial reviews suggest that the new interface would not improve graphic performance compared to earlier PCIe 2.0, which, at the time of writing, is still under-utilized. However, the new interface would prove advantageous when used for general purpose computing with technologies like OpenCLCUDA and C++ 


Source: http://en.wikipedia.org/wiki/PCI_Express#PCI_Express_2.0

PCI-E 3.0 doubles the amount of bandwidth compared to PCI-E 2.0, which means it can carry twice the data that PCI-E 2.0 can. Right now the extra bandwidth is unneeded because current graphics cards aren't fast enough to utilize the extra bandwidth. PCI-E 2.0 X16 is more than what is needed for current graphics cards, and you'll only see a difference of 3-5 frames per second between PCI-E 2.0 X8 and PCI-E 2.0 X16.

Right now there is really no reason for PCI-E 3.0 unless you're going to be running some crazy fast PCI-E based SSDs or something. It will probably be utilized more in the future though, so it might be nice just for future proofing.

For GPU nothing unless you're talking about Crossfire/SLI where most of the boards drop to 8x 8x, then you can get some performance jump as PCIe 3.0 8x is the same as 2.0 16x

From what I've read, you'll likely lose only one FPS, and this is in the worst case.

Yeah, a drop to 8x on PCI-E 2.0 won't really hurt your performance, and if it does it will only usually be between 1-5 fps.

PCI-E 3.0 from what I understand is more or less geard towards 3-way GPU setup on a dual channel system.  8x8x4x having the effective bandwith of 16x16x8.  Whereas it was previously a complete waste to run a third gpu at 4x on the 2.0 standard.