New EPYC Genoa Announced! Benchmarks From Level1Techs

Hello! Exciting news in the world of EPYC computing!

AMD just had their presentation about the new EPYC Genoa CPUs! Wendell was there live, and we have the Linux scoop with a video (coming soon, will update with a link) & Phoronix benchmarks!

The technical document mentioned in the video will be released on the AMD website. The link will be updated when AMD decides to post it :slight_smile:

Level1Techs Release Video

AMD Release Presentation

Download benchmarks individually or with a bulk RAR at the end for all.

Note: 2x Intel Xeon Platinum 8380 testing with a Supermicro X12DPi-NT6 v1.00 (1.1b BIOS) and ASPEED on Fedora Linux 36

Phoronix Test Suite Downloads

Core-Core Latency

EPYC Core-Core Latency in Nanoseconds:


oneDNN

OneDNN on my epyc? Its more likely than you think.

Highlights

Screenshot 2022-11-09 173613

Screenshot 2022-11-09 173645

Screenshot 2022-11-09 173704 (1)

Screenshot 2022-11-09 173704 (1)

All oneDNN Results

pts-memory

pts-phpbench

SVT-VP9, SVT-AVI, SVT-HVEC

All Other Benchmarks

System Info

NAMD

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dav1d

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Coremark

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POV-Ray

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Stockfish

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asmFish

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Timed LLVM Compilation

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C-Ray

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Blender

Test 1

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Test 2

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Test 3

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Test 4

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Test 5

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PyBench

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Appleseed

Part 1


Part 2

17 Likes

Ifs baaanaanaaaaaaas

10 Likes

Just when I could brag that my NAS has the most badass processor on the planet, AMD releases this 6096 pin biblical monster :sweat_smile: :star_struck:

Do I want one ? Fo shure ! Can I justify buying one ? No, not even the voices in my head are with me on this :grin:

4 Likes

Where are the technical documents referenced in the video?

Would be interesting to see if AMD would consider launching an SoC solution based on Zen4 EPYC, like they did with the 3000 series SoC. Imagine an m-ITX system based on EPYC 7000 in an HTPC case :exploding_head:

(though truthfully, I doubt it’ll fit the 170x170mm board size, given how big Genoa chips actually are :upside_down_face: )

They’ll be on AMD’s website when they do post them. I will update with a link when they post it :slight_smile:

1 Like

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Wish I had an excuse to purchase one! It could hold a good chunk of my media collection just in RAM :joy:

1 Like

What I’m expecting to be a game changer moving forward is the implimentation of CXL support.

I suspect this is going to be advancing data centers to be able to disaggregate equipment to spread the power usage so it isn’t so rack concetrated.

So Wendall, any idea on why the EPYC tech is limited to 2 sockets ?

I may have missed why Intel supports up to 8 sockets but not AMD.

It’s a design choice. With two sockets, you have 64 lanes as an interconnect between the CPUs. With 4 sockets, you need to either split the bandwidth or sacrifice even more lanes. And two (the ones opposing each other)sockets will have very high latencies between each other.

It’s not very efficient to go beyond two sockets. You get a net increase in horsepower, but the scaling leaves much to be desired. Always was bad in 4-socket systems or 8-socket systems. You end up with 2-3x the cost for like 50% increase in processing power. And we now have 96 cores per CPU, we don’t need mass sockets to get enough cores anymore.

People buy “cheap” 1/2-socket systems and buy a lot of them, rather than putting more sockets into a single node. Intel is still selling 4/8-socket systems but the customer base is shrinking. Horizontal scaling in 1U or 2U rack units is the name of the game, rather than vertical scaling with 4-100 CPUs per machine we’ve seen in the past.

And we also have per core licensing today. In the distant past you payed per server. So it was beneficial to get as much CPU power into a single server as possible, to maximize the use of your license. With per socket licensing, things changed. With per core licensing, you do not want inefficient cores with bad scaling in your systems.

5 Likes

The same reason AMD chose not to created a more scale-up CPU at the cost of overall efficiency is the reason CXL is going to be limited in utility (at least limited compared to the people saying it will usher in the widespread adoption of composable infrastructure).

Moving high speed/low latency signals far costs too much in power to be viable, I think we’re going to see a paradigm akin to the inverse of CXL in the future with the aggregation of the power hungry dies close and closer to reduce energy and increase performance like the upcoming MI300.

1 Like

Thanks for the replies, I was wondering if it was a design and/or cost savings choice and it looks like both.

What was the server Wendell showed off in the video?

Wasn’t that the Titanite Validation Platform for SP5 that AMD ships ?