Hello,
Is there a way to fix the CCX/L3-cache configuration for chips with disabled cores? (like 2920x, 2970wx)
I’m trying to passthrough an entire die/node and I get 4+2 (instead of 3+3) in the guest, by using EPYC as cpu model.
Thanks.
Post XML?
I’m heading off for the night, I’ll have a look at it in the morning.
<domain type="kvm">
<name>steamos</name>
<uuid>93ff05fa-2a50-4ed2-b17a-1a45bb3bb993</uuid>
<metadata>
<libosinfo:libosinfo xmlns:libosinfo="http://libosinfo.org/xmlns/libvirt/domain/1.0">
<libosinfo:os id="http://debian.org/debian/8"/>
</libosinfo:libosinfo>
</metadata>
<memory unit="KiB">10240000</memory>
<currentMemory unit="KiB">10240000</currentMemory>
<vcpu placement="static">12</vcpu>
<cputune>
<vcpupin vcpu="0" cpuset="6"/>
<vcpupin vcpu="1" cpuset="18"/>
<vcpupin vcpu="2" cpuset="7"/>
<vcpupin vcpu="3" cpuset="19"/>
<vcpupin vcpu="4" cpuset="8"/>
<vcpupin vcpu="5" cpuset="20"/>
<vcpupin vcpu="6" cpuset="9"/>
<vcpupin vcpu="7" cpuset="21"/>
<vcpupin vcpu="8" cpuset="10"/>
<vcpupin vcpu="9" cpuset="22"/>
<vcpupin vcpu="10" cpuset="11"/>
<vcpupin vcpu="11" cpuset="23"/>
<emulatorpin cpuset="1-2"/>
</cputune>
<os>
<type arch="x86_64" machine="pc-i440fx-4.0">hvm</type>
<loader readonly="yes" type="pflash">/usr/share/ovmf/x64/OVMF_CODE.fd</loader>
<nvram>/var/lib/libvirt/qemu/nvram/steamos_VARS.fd</nvram>
<boot dev="hd"/>
</os>
<features>
<acpi/>
<apic/>
<kvm>
<hidden state="on"/>
</kvm>
<vmport state="off"/>
</features>
<cpu mode="custom" match="exact" check="partial">
<model fallback="allow">EPYC</model>
<topology sockets="1" cores="6" threads="2"/>
</cpu>
<clock offset="utc">
<timer name="rtc" tickpolicy="catchup"/>
<timer name="pit" tickpolicy="delay"/>
<timer name="hpet" present="no"/>
</clock>
<on_poweroff>destroy</on_poweroff>
<on_reboot>restart</on_reboot>
<on_crash>destroy</on_crash>
<pm>
<suspend-to-mem enabled="no"/>
<suspend-to-disk enabled="no"/>
</pm>
<devices>
<emulator>/usr/bin/qemu-system-x86_64</emulator>
<disk type="block" device="disk">
<driver name="qemu" type="raw" cache="none" io="native"/>
<source dev="/dev/vgw/steamos"/>
<target dev="vda" bus="virtio"/>
<address type="pci" domain="0x0000" bus="0x00" slot="0x09" function="0x0"/>
</disk>
<controller type="usb" index="0" model="qemu-xhci" ports="15">
<address type="pci" domain="0x0000" bus="0x00" slot="0x03" function="0x0"/>
</controller>
<controller type="pci" index="0" model="pci-root"/>
<controller type="sata" index="0">
<address type="pci" domain="0x0000" bus="0x00" slot="0x04" function="0x0"/>
</controller>
<controller type="ide" index="0">
<address type="pci" domain="0x0000" bus="0x00" slot="0x01" function="0x1"/>
</controller>
<interface type="bridge">
<mac address="52:54:00:f2:f9:ef"/>
<source bridge="br0"/>
<model type="virtio"/>
<address type="pci" domain="0x0000" bus="0x00" slot="0x02" function="0x0"/>
</interface>
<serial type="pty">
<target type="isa-serial" port="0">
<model name="isa-serial"/>
</target>
</serial>
<console type="pty">
<target type="serial" port="0"/>
</console>
<input type="mouse" bus="ps2"/>
<input type="keyboard" bus="ps2"/>
<hostdev mode="subsystem" type="pci" managed="yes">
<driver name="vfio"/>
<source>
<address domain="0x0000" bus="0x09" slot="0x00" function="0x0"/>
</source>
<address type="pci" domain="0x0000" bus="0x00" slot="0x05" function="0x0"/>
</hostdev>
<hostdev mode="subsystem" type="pci" managed="yes">
<source>
<address domain="0x0000" bus="0x09" slot="0x00" function="0x1"/>
</source>
<address type="pci" domain="0x0000" bus="0x00" slot="0x06" function="0x0"/>
</hostdev>
<hostdev mode="subsystem" type="pci" managed="yes">
<source>
<address domain="0x0000" bus="0x44" slot="0x00" function="0x3"/>
</source>
<address type="pci" domain="0x0000" bus="0x00" slot="0x0a" function="0x0"/>
</hostdev>
<memballoon model="virtio">
<address type="pci" domain="0x0000" bus="0x00" slot="0x07" function="0x0"/>
</memballoon>
<rng model="virtio">
<backend model="random">/dev/urandom</backend>
<address type="pci" domain="0x0000" bus="0x00" slot="0x08" function="0x0"/>
</rng>
</devices>
</domain>Sorry it took so long to get back to you on this.
I can’t say why this cache configuration is showing up this way. You’ve got all the correct configuration I would expect to see in a VM. It’s possible that’s how it is on the host CPU. I don’t know what the topology of the host looks like, so I can’t say for sure. (I would start by comparing that)
Thanks for the reply.
I can’t post a screenshot right now, but the host topology looks ok; what you would expect from a 2920x. (which is what I have right now)
2 numa nodes, each with 6 cores, split into 2 3-core CCXs, each with 8MB L3 cache.
A few people on reddit reported similar issues, one suggesting to force it by configuring 2 sockets (each with 3 cores) but I would like to avoid that. (especially since I’m mostly using windows 10 home, which doesn’t support dual socket systems)
I played a little with this code, which should be responsible with building the topology (and in my tests it looks like it does try to create a 3+3 topo, with the correct L3 cache) but most of this values seem to be ignored or overwritten once I enable TOPOEXT. (it receives the topology from the kernel … ? I don’t know … it’s out of my league)
Could someone with a 3900x try this? (passthrough an entire die and check the L3 config on the guest)
Or maybe already did and share the results?
Thanks.