RISC is only half-arsed.
I present to you…
OISC
The one instruction computer. Apparently you can build a general purpose CPU with one instruction.
Which means… no need for opcodes (there’s only one option for instructions 
). Which makes fetching instructions … not a thing. It’s always the same instruction.
Sure, doing complex operations may be a bit of a pain… but…
In a similar vein you might find this talk interesting. its a compiler that has been built that uses the mov and only the mov instruction for everything.
the compiler its self can only be found on github here:
I implemented a URISC computer in Chisel as a project for school, and a rudimentary assembler. I added a few more instructions to make memory load/store easier to implement, and the assembler made heavy use of macros to fake a more user friendly set of instructions. I meant to get it running on an FPGA eventually but due to time constraints I didn’t finish writing the ROM code and only ever ran it in the simulator. Cool stuff though.
So what you’re telling me is theres a cpu out there based only in buffer overfrows?
Interesting. So if you take a bunch of OISCs and put them together into a single package, would it run faster or slower than a comparable unit with multiple instructions in a single package?
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