Like some others in this forum I also have the problem that both GPUs are in the same IOMMU group.
ACS & VT-d seems to be enabled in the BIOS Settings.
Is there anything I can try before switching to a kernel with acs patch?
Setup:
OS: Arch Linux x86_64
CPU: Intel i7-8086K (12) @ 5.000GHz
Motherboard: Asus maximus x hero
GPU 1: NVIDIA GeForce RTX 3090
GPU 2: NVIDIA GeForce GTX 980
IOMMU Groups:
IOMMU Group 0:
00:00.0 Host bridge [0600]: Intel Corporation 8th Gen Core Processor Host Bridge/DRAM Registers [8086:3ec2] (rev 07)
IOMMU Group 1:
00:01.0 PCI bridge [0604]: Intel Corporation 6th-10th Gen Core Processor PCIe Controller (x16) [8086:1901] (rev 07)
00:01.1 PCI bridge [0604]: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x8) [8086:1905] (rev 07)
01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GA102 [GeForce RTX 3090] [10de:2204] (rev a1)
01:00.1 Audio device [0403]: NVIDIA Corporation GA102 High Definition Audio Controller [10de:1aef] (rev a1)
02:00.0 VGA compatible controller [0300]: NVIDIA Corporation GM204 [GeForce GTX 980] [10de:13c0] (rev a1)
02:00.1 Audio device [0403]: NVIDIA Corporation GM204 High Definition Audio Controller [10de:0fbb] (rev a1)
IOMMU Group 2:
00:02.0 VGA compatible controller [0300]: Intel Corporation CometLake-S GT2 [UHD Graphics 630] [8086:3e92]
IOMMU Group 3:
00:14.0 USB controller [0c03]: Intel Corporation 200 Series/Z370 Chipset Family USB 3.0 xHCI Controller [8086:a2af]
IOMMU Group 4:
00:16.0 Communication controller [0780]: Intel Corporation 200 Series PCH CSME HECI #1 [8086:a2ba]
IOMMU Group 5:
00:17.0 SATA controller [0106]: Intel Corporation 200 Series PCH SATA controller [AHCI mode] [8086:a282]
IOMMU Group 6:
00:1b.0 PCI bridge [0604]: Intel Corporation 200 Series PCH PCI Express Root Port #17 [8086:a2e7] (rev f0)
IOMMU Group 7:
00:1c.0 PCI bridge [0604]: Intel Corporation 200 Series PCH PCI Express Root Port #1 [8086:a290] (rev f0)
IOMMU Group 8:
00:1c.4 PCI bridge [0604]: Intel Corporation 200 Series PCH PCI Express Root Port #5 [8086:a294] (rev f0)
IOMMU Group 9:
00:1c.6 PCI bridge [0604]: Intel Corporation 200 Series PCH PCI Express Root Port #7 [8086:a296] (rev f0)
IOMMU Group 10:
00:1d.0 PCI bridge [0604]: Intel Corporation 200 Series PCH PCI Express Root Port #9 [8086:a298] (rev f0)
IOMMU Group 11:
00:1f.0 ISA bridge [0601]: Intel Corporation Z370 Chipset LPC/eSPI Controller [8086:a2c9]
00:1f.2 Memory controller [0580]: Intel Corporation 200 Series/Z370 Chipset Family Power Management Controller [8086:a2a1]
00:1f.3 Audio device [0403]: Intel Corporation 200 Series PCH HD Audio [8086:a2f0]
00:1f.4 SMBus [0c05]: Intel Corporation 200 Series/Z370 Chipset Family SMBus Controller [8086:a2a3]
IOMMU Group 12:
00:1f.6 Ethernet controller [0200]: Intel Corporation Ethernet Connection (2) I219-V [8086:15b8]
IOMMU Group 13:
03:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808]
IOMMU Group 14:
05:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM2142 USB 3.1 Host Controller [1b21:2142]
IOMMU Group 15:
06:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM2142 USB 3.1 Host Controller [1b21:2142]
Full BIOS Settings Dump
[2021/07/28 17:33:05]
Ai Overclock Tuner [Auto]
ASUS MultiCore Enhancement [Auto]
SVID Behavior [Auto]
AVX Instruction Core Ratio Negative Offset [Auto]
CPU Core Ratio [Auto]
BCLK Frequency : DRAM Frequency Ratio [Auto]
DRAM Odd Ratio Mode [Enabled]
DRAM Frequency [Auto]
Xtreme Tweaking [Disabled]
TPU [Keep Current Settings]
CPU SVID Support [Auto]
CPU Core/Cache Current Limit Max. [Auto]
CPU Graphics Current Limit [Auto]
Ring Down Bin [Auto]
Min. CPU Cache Ratio [Auto]
Max CPU Cache Ratio [Auto]
Max. CPU Graphics Ratio [Auto]
BCLK Aware Adaptive Voltage [Auto]
CPU Core/Cache Voltage [Auto]
DRAM Voltage [Auto]
CPU VCCIO Voltage [Auto]
CPU System Agent Voltage [Auto]
PLL Termination Voltage [Auto]
CPU Graphics Voltage Mode [Auto]
PCH Core Voltage [Auto]
CPU Standby Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL7 [Auto]
Realtime Memory Timing [Disabled]
FCLK Frequency for Early Power On [Auto]
Initial BCLK Frequency [Auto]
BCLK Amplitude [Auto]
BCLK Slew Rate [Auto]
BCLK Spread Spectrum [Auto]
BCLK Frequency Slew Rate [Auto]
DRAM VTT Voltage [Auto]
VPPDDR Voltage [Auto]
DMI Voltage [Auto]
Core PLL Voltage [Auto]
Internal PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
PLL Bandwidth [Auto]
Eventual DRAM Voltage [Auto]
Eventual CPU Standby Voltage [Auto]
Eventual PLL Termination Voltage [Auto]
Eventual DMI Voltage [Auto]
Maximus Tweak [Auto]
DRAM CAS# Latency [Auto]
DRAM RAS# to CAS# Delay [Auto]
DRAM RAS# ACT Time [Auto]
DRAM Command Rate [Auto]
DRAM RAS# to RAS# Delay L [Auto]
DRAM RAS# to RAS# Delay S [Auto]
DRAM REF Cycle Time [Auto]
DRAM Refresh Interval [Auto]
DRAM WRITE Recovery Time [Auto]
DRAM READ to PRE Time [Auto]
DRAM FOUR ACT WIN Time [Auto]
DRAM WRITE to READ Delay [Auto]
DRAM WRITE to READ Delay L [Auto]
DRAM WRITE to READ Delay S [Auto]
DRAM CKE Minimum Pulse Width [Auto]
DRAM Write Latency [Auto]
tRDRD_sg [Auto]
tRDRD_dg [Auto]
tRDWR_sg [Auto]
tRDWR_dg [Auto]
tWRWR_sg [Auto]
tWRWR_dg [Auto]
tWRRD_sg [Auto]
tWRRD_dg [Auto]
tRDRD_dr [Auto]
tRDRD_dd [Auto]
tRDWR_dr [Auto]
tRDWR_dd [Auto]
tWRWR_dr [Auto]
tWRWR_dd [Auto]
tWRRD_dr [Auto]
tWRRD_dd [Auto]
TWRPRE [Auto]
TRDPRE [Auto]
tREFIX9 [Auto]
OREF_RI [Auto]
MRC Fast Boot [Auto]
DRAM CLK Period [Auto]
Memory Scrambler [Enabled]
Channel A DIMM Control [Enable both DIMMs]
Channel B DIMM Control [Enable both DIMMs]
MCH Full Check [Auto]
Mem Over Clock Fail Count [Auto]
Training Profile [Auto]
DLLBwEn [Auto]
DRAM SPD Write [Disabled]
XTU Setting [Auto]
DRAM RTL INIT value [Auto]
DRAM RTL (CHA DIMM0 Rank0) [Auto]
DRAM RTL (CHA DIMM0 Rank1) [Auto]
DRAM RTL (CHA DIMM1 Rank0) [Auto]
DRAM RTL (CHA DIMM1 Rank1) [Auto]
DRAM RTL (CHB DIMM0 Rank0) [Auto]
DRAM RTL (CHB DIMM0 Rank1) [Auto]
DRAM RTL (CHB DIMM1 Rank0) [Auto]
DRAM RTL (CHB DIMM1 Rank1) [Auto]
DRAM IOL (CHA DIMM0 Rank0) [Auto]
DRAM IOL (CHA DIMM0 Rank1) [Auto]
DRAM IOL (CHA DIMM1 Rank0) [Auto]
DRAM IOL (CHA DIMM1 Rank1) [Auto]
DRAM IOL (CHB DIMM0 Rank0) [Auto]
DRAM IOL (CHB DIMM0 Rank1) [Auto]
DRAM IOL (CHB DIMM1 Rank0) [Auto]
DRAM IOL (CHB DIMM1 Rank1) [Auto]
CHA IO_Latency_offset [Auto]
CHB IO_Latency_offset [Auto]
CHA RFR delay [Auto]
CHB RFR delay [Auto]
ODT RTT WR (CHA) [Auto]
ODT RTT PARK (CHA) [Auto]
ODT RTT NOM (CHA) [Auto]
ODT RTT WR (CHB) [Auto]
ODT RTT PARK (CHB) [Auto]
ODT RTT NOM (CHB) [Auto]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
Data Rising Slope [Auto]
Data Rising Slope Offset [Auto]
Cmd Rising Slope [Auto]
Cmd Rising Slope Offset [Auto]
Ctl Rising Slope [Auto]
Ctl Rising Slope Offset [Auto]
Clk Rising Slope [Auto]
Clk Rising Slope Offset [Auto]
Data Falling Slope [Auto]
Data Falling Slope Offset [Auto]
Cmd Falling Slope [Auto]
Cmd Falling Slope Offset [Auto]
Ctl Falling Slope [Auto]
Ctl Falling Slope Offset [Auto]
Clk Falling Slope [Auto]
Clk Falling Slope Offset [Auto]
CPU Load-line Calibration [Auto]
CPU Current Capability [Auto]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Auto]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Auto]
CPU VRM Thermal Control [Auto]
CPU Graphics Load-line Calibration [Auto]
CPU Graphics Current Capability [Auto]
CPU Graphics Switching Frequency [Auto]
CPU Graphics Power Phase Control [Auto]
DRAM Current Capability [100%]
DRAM Switching Frequency [Auto]
CPU Core/Cache Boot Voltage [Auto]
DMI Boot Voltage [Auto]
Core PLL Boot Voltage [Auto]
CPU System Agent Boot Voltage [Auto]
CPU VCCIO Boot Voltage [Auto]
PLL Termination Boot voltage [Auto]
CPU Standby Boot Voltage [Auto]
Intel(R) SpeedStep(tm) [Auto]
Turbo Mode [Enabled]
Long Duration Package Power Limit [Auto]
Package Power Time Window [Auto]
Short Duration Package Power Limit [Auto]
IA AC Load Line [Auto]
IA DC Load Line [Auto]
TVB Voltage Optimizations [Auto]
Hyper-Threading [Enabled]
Thermal Monitor [Enabled]
Active Processor Cores [All]
Intel Virtualization Technology [Enabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Enabled]
Boot performance mode [Auto]
SW Guard Extensions (SGX) [Software Controlled]
Tcc Offset Time Window [Auto]
Execute Disable Bit [Enabled]
SMM Code Access Check [Enabled]
SMM Use Delay Indication [Enabled]
SMM Use Block Indication [Enabled]
Intel(R) SpeedStep(tm) [Auto]
Turbo Mode [Enabled]
CPU C-states [Auto]
CFG Lock [Disabled]
Intel(R) Speed Shift Technology [Enabled]
Number of P states [0]
Acoustic Noise Mitigation [Disabled]
Disable Fast PKG C State Ramp for IA Domain [FALSE]
Slow Slew Rate for IA Domain [Fast/2]
Disable Fast PKG C State Ramp for GT Domain [FALSE]
Slow Slew Rate for GT Domain [Fast/2]
Disable Fast PKG C State Ramp for SA Domain [FALSE]
Slow Slew Rate for SA Domain [Fast/2]
Configurable TDP Boot Mode [Nominal]
Configurable TDP Lock [Disabled]
CTDP BIOS control [Disabled]
Power Limit 1 [0]
Power Limit 2 [0]
Power Limit 1 Time Window [0]
ConfigTDP Turbo Activation Ratio [0]
Overclocking Lock [Disabled]
PCI Express Native Power Management [Disabled]
PCH DMI ASPM [Disabled]
ASPM [Disabled]
DMI Link ASPM Control [Disabled]
PEG - ASPM [Disabled]
PTID Support [Enabled]
PECI Access Method [Direct I/O]
PCI Express Native Power Management [Disabled]
BDAT ACPI Table Support [Disabled]
Wake system from S5 [Disabled]
ACPI Debug [Disabled]
Low Power S0 Idle Capability [Disabled]
Lpit Recidency Counter [SLP S0]
PCI Delay Optimization [Disabled]
ZpODD Support [Disabled]
Type C Support [Enabled]
PEP CPU [Enabled]
PEP Graphics [Enabled]
PEP ISP [Disabled]
PEP SATA Controller [Enabled]
PEP RAID VOL0 [Disabled]
PEP SATA PORT0 [Disabled]
PEP SATA PORT1 [Disabled]
PEP SATA PORT2 [Disabled]
PEP SATA PORT3 [Disabled]
PEP SATA PORT4 [Disabled]
PEP SATA PORT5 [Disabled]
PEP SATA NVM1 [Disabled]
PEP SATA NVM2 [Disabled]
PEP SATA NVM3 [Disabled]
PEP UART [Enabled]
PEP I2C0 [Enabled]
PEP I2C1 [Enabled]
PEP I2C2 [Enabled]
PEP I2C3 [Enabled]
PEP I2C4 [Enabled]
PEP I2C5 [Enabled]
PEP SPI [Enabled]
PEP XHCI [Enabled]
PEP Audio [Enabled]
PEP EMMC [Enabled]
PEP SDXC [Enabled]
VT-d [Enabled]
Primary Display [IGFX]
iGPU Multi-Monitor [Disabled]
RC6(Render Standby) [Auto]
DVMT Pre-Allocated [64M]
DMI Max Link Speed [Auto]
PCIEX16/X8_1 Link Speed [Auto]
PCIEX8_2 Link Speed [Auto]
PCIe Spread Spectrum Clocking [Auto]
IOAPIC 24-119 Entries [Enabled]
PCIe Speed [Gen3]
SATA Controller(s) [Enabled]
SATA Mode Selection [AHCI]
S.M.A.R.T. Status Check [Enabled]
Aggressive LPM Support [Disabled]
SATA6G_1(Gray) [Enabled]
Hot Plug [Disabled]
SATA6G_2(Gray) [Enabled]
Hot Plug [Disabled]
SATA6G_3(Gray) [Enabled]
Hot Plug [Disabled]
SATA6G_4(Gray) [Enabled]
Hot Plug [Disabled]
SATA6G_5(Gray) [Enabled]
Hot Plug [Disabled]
SATA6G_6(Gray) [Enabled]
Hot Plug [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 0 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 1 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 2 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 3 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 4 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 5 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Port 6 [Enabled]
Hot Plug [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 6 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Port 7 [Enabled]
Hot Plug [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 7 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
PCI Express Root Port 1 [Enabled]
Topology [Unknown]
ASPM [Disabled]
L1 Substates [Disabled]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE1 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE1 LTR Lock [Disabled]
PCIE1 CLKREQ Mapping Override [Default]
PCI Express Root Port 2 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE2 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE2 LTR Lock [Disabled]
PCIE2 CLKREQ Mapping Override [Default]
PCI Express Root Port 3 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE3 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE3 LTR Lock [Disabled]
PCIE3 CLKREQ Mapping Override [Default]
PCI Express Root Port 4 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE4 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE4 LTR Lock [Disabled]
PCIE4 CLKREQ Mapping Override [Default]
PCI Express Root Port 5 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE5 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE5 LTR Lock [Disabled]
PCIE5 CLKREQ Mapping Override [Default]
PCI Express Root Port 6 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE6 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE6 LTR Lock [Disabled]
PCIE6 CLKREQ Mapping Override [Default]
PCI Express Root Port 7 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [7]
Reserved Memory [17]
Reserved I/O [16]
PCH PCIE7 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE7 LTR Lock [Disabled]
PCIE7 CLKREQ Mapping Override [Default]
PCI Express Root Port 8 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [7]
Reserved Memory [17]
Reserved I/O [8]
PCH PCIE8 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE8 LTR Lock [Disabled]
PCIE8 CLKREQ Mapping Override [Default]
PCI Express Root Port 9 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE9 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE9 LTR Lock [Disabled]
PCIE9 CLKREQ Mapping Override [Default]
PCI Express Root Port 10 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE10 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE10 LTR Lock [Disabled]
PCIE10 CLKREQ Mapping Override [Default]
PCI Express Root Port 11 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE11 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE11 LTR Lock [Disabled]
PCIE11 CLKREQ Mapping Override [Default]
PCI Express Root Port 12 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE12 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE12 LTR Lock [Disabled]
PCIE12 CLKREQ Mapping Override [Default]
PCI Express Root Port 13 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE13 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE13 LTR Lock [Disabled]
PCIE13 CLKREQ Mapping Override [Default]
PCI Express Root Port 14 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE14 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE14 LTR Lock [Disabled]
PCIE14 CLKREQ Mapping Override [Default]
PCI Express Root Port 15 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE15 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE15 LTR Lock [Disabled]
PCIE15 CLKREQ Mapping Override [Default]
PCI Express Root Port 16 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE16 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE16 LTR Lock [Disabled]
PCIE16 CLKREQ Mapping Override [Default]
PCI Express Root Port 17 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE17 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE17 LTR Lock [Disabled]
PCIE17 CLKREQ Mapping Override [Default]
PCI Express Root Port 18 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE18 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE18 LTR Lock [Disabled]
PCIE18 CLKREQ Mapping Override [Default]
PCI Express Root Port 19 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE19 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE19 LTR Lock [Disabled]
PCIE19 CLKREQ Mapping Override [Default]
PCI Express Root Port 20 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE20 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE20 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 21 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE21 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE21 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 22 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE22 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE22 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 23 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE23 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE23 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 24 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE24 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE24 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
Audio DSP [Disabled]
HDA-Link Codec Select [Platform Onboard]
iDisplay Audio Disconnect [Disabled]
PME Enable [Disabled]
SerialIO timing parameters [Disabled]
TPM Device Selection [dTPM]
PTP aware OS [PTP Aware]
Me FW Image Re-Flash [Disabled]
Local FW Update [Enabled]
HECI Timeouts [Enabled]
Force ME DID Init Status [Disabled]
CPU Replaced Polling Disable [Disabled]
ME DID Message [Enabled]
HECI Retry Disable [Disabled]
HECI Message check Disable [Disabled]
MBP HOB Skip [Disabled]
HECI2 Interface Communication [Disabled]
KT Device [Enabled]
IDER Device [Enabled]
End Of Post Message [Send in DXE]
D0I3 Setting for HECI Disable [Disabled]
Select Camera [Ivcam]
Delay needed for Ivcam power on [0]
Delay needed for Ivcam power off [0]
Rotation [0]
DFU support [Disabled]
Wake support [Disabled]
tRd2RdSG [0]
tRd2RdDG [0]
tRd2RdDR [0]
tRd2RdDD [0]
tRd2WrSG [0]
tRd2WrDG [0]
tRd2WrDR [0]
tRd2WrDD [0]
tWr2RdSG [0]
tWr2RdDG [0]
tWr2RdDR [0]
tWr2RdDD [0]
tWr2WrSG [0]
tWr2WrDG [0]
tWr2WrDR [0]
tWr2WrDD [0]
Core PLL Voltage Offset [0]
GT PLL Voltage Offset [0]
Ring PLL Voltage Offset [0]
System Agent PLL Voltage Offset [0]
Memory Controller PLL Voltage Offset [0]
ASF support [Enabled]
USB Provisioning of AMT [Disabled]
Activate Remote Assistance Process [Disabled]
CIRA Timeout [0]
PET Progress [Enabled]
WatchDog [Disabled]
OS Timer [0]
BIOS Timer [0]
Secure Erase mode [Simulated]
Force Secure Erase [Disabled]
MEBx hotkey Pressed [Disabled]
MEBx Selection Screen [Disabled]
Hide Unconfigure ME Confirmation Prompt [Disabled]
MEBx OEM Debug Menu Enable [Disabled]
Unconfigure ME [Disabled]
Non-UI Mode Resolution [Auto]
UI Mode Resolution [Auto]
Graphics Mode Resolution [Auto]
Security Device Support [Enable]
Security Device Support [Enable]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
TPM2.0 UEFI Spec Version [TCG_2]
Physical Presence Spec Version [1.3]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Onboard LED [Enabled]
Q-Code LED Function [POST Code Only]
ErP Ready [Disabled]
Restore AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
HD Audio Controller [Enabled]
PCIEX4_3 Bandwidth [X2 Mode]
M.2_1 Configuration: [Auto][SATA mode][PCIE mode] [Auto]
M.2_2 Configuration [X2]
Asmedia Back USB 3.1 Controller [Enabled]
Asmedia Front USB 3.1 Controller [Enabled]
USB Type C Power Switch [Auto]
When system is in working state [On]
When system is in sleep, hibernate or soft off states [On]
Intel LAN Controller [Enabled]
Intel LAN PXE Option ROM [Disabled]
Detect Non-Compliance Device [Disabled]
Network Stack [Disabled]
Legacy USB Support [Enabled]
USB Keyboard and Mouse Simulator [Disabled]
SanDisk Cruzer 1.26 [Auto]
U31G2_EC2 [Enabled]
U31G2_EA1 [Enabled]
U31G1_1 [Enabled]
U31G1_2 [Enabled]
U31G1_3 [Enabled]
U31G1_4 [Enabled]
U31G1_5 [Enabled]
U31G1_6 [Enabled]
USB_7 [Enabled]
USB_8 [Enabled]
USB_9 [Enabled]
USB_10 [Enabled]
USB_11 [Enabled]
USB_12 [Enabled]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor Temperature [Monitor]
EXT_Sensor1 Temperature [Monitor]
EXT_Sensor2 Temperature [Monitor]
EXT_Sensor3 Temperature [Monitor]
Water In T Sensor [Monitor]
Water Out T Sensor [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
AIO PUMP Speed [Monitor]
HAMP Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
W_PUMP+ Speed [Monitor]
Extension Fan 1 Speed [Monitor]
Extension Fan 2 Speed [Monitor]
Extension Fan 3 Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Auto]
CPU Fan Step Up [0 sec]
CPU Fan Step Down [0 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Standard]
AIO_PUMP/W_PUMP+ Control [Disabled]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [0 sec]
Chassis Fan 1 Step Down [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Step Up [0 sec]
Chassis Fan 2 Step Down [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
Chassis Fan 3 Q-Fan Control [Auto]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Step Up [0 sec]
Chassis Fan 3 Step Down [0 sec]
Chassis Fan 3 Speed Low Limit [200 RPM]
Chassis Fan 3 Profile [Standard]
HAMP Fan Control [Auto]
HAMP Fan Source [CPU]
HAMP Fan Step Up [0 sec]
HAMP Fan Step Down [0 sec]
HAMP Fan Speed Low Limit [200 RPM]
HAMP Fan Profile [Standard]
Extension Fan 1 Q-Fan Control [DC Mode]
Extension Fan 1 Q-Fan Source [CPU]
Extension Fan 1 Speed Low Limit [200 RPM]
Extension Fan 1 Profile [Standard]
Extension Fan 2 Q-Fan Control [DC Mode]
Extension Fan 2 Q-Fan Source [CPU]
Extension Fan 2 Speed Low Limit [200 RPM]
Extension Fan 2 Profile [Standard]
Extension Fan 3 Q-Fan Control [DC Mode]
Extension Fan 3 Q-Fan Source [CPU]
Extension Fan 3 Speed Low Limit [200 RPM]
Extension Fan 3 Profile [Standard]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Above 4G Decoding [Disabled]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Enabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
Launch CSM [Enabled]
Boot Device Control [UEFI and Legacy OPROM]
Boot from Network Devices [Legacy only]
Boot from Storage Devices [Legacy only]
Boot from PCI-E/PCI Expansion Devices [Legacy only]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [1]
Profile Name []
Save to Profile [1]
Bus Interface [PCIEX16/X8_1]