Asrock amd x570 creator mega info

Hardware Hub Motherboards
19

Here’s my I/O breakdown based on the user manuals on Asrock’s website and Buildzoid’s video:

  • The three PCIe x16 slots can be configured as 16/0/4 or 8/8/4 with 1 or (2 & 3) cards respectively.

  • PCIE1 and PCIE4 are from the CPU
    PCIE6 comes from the chipset and is quite possibly shared with M2_2
    PCIE2, 3 & 5 come from the X570 as determined later on

  • Both M2 slots are PCIe x4.
    M2_1 is connected to the CPU and is always available
    M2_2 is connected to the chipset and also provides SATA capability for this slot

The Japanese manual indicates that PCIE5 (6?) is disabled when M2_3 (2?) is populated.
The above statement, and any mention of Thunderbolt are missing from the English manual.

Ryzen 3000 provides 20 usable PCIe 4.0 lanes, these are accounted for in PCIE1, PCIE4 and M2_1

This means everything else must come from X570, which has 16 downstream PCIe Gen 4 lanes so long as no more than the correct 4 SATA ports are used.

Lanes counts are:

  • 4 lanes for M2_2, and possibly PCIE6 -> PCIe Gen 4
  • 2 lanes for the M.2 E-key hosting the WiFi -> PCIe Gen 3
  • 2 lanes for the AQC107 -> PCIe Gen 3 (assumed from Gigabyte GC-AQC107)
  • 4 lanes for Titan Ridge -> PCIe Gen 3
  • 3 lanes for PCIE2, 3 & 5 -> assume PCIe Gen 2
  • 1 lane for the Intel I211AT -> PCIe Gen 2
  • 2x1 lanes for the dual ASM1061 -> PCIe Gen 2

This is a total of 18 lanes to drive.

Mass market PCIe Gen 4 packet switches are expensive at the moment, so we’ll say that anything Gen 4 or Gen 3 is directly connected to the X570. This consumes 12 lanes, leaving us with 4 lanes to drive into the remaining 6 PCIe Gen 2.0 x1 devices.

How might that be done? Without seeing the back of the board, I’m going to assume that the chip between PCIE3 and the battery in Buildzoid’s video is some sort of PCIe switch, perhaps something like the Asmedia ASM2812. I can’t say for certain, but from the shots on Asrock’s website and the press photos from May the chip is clearly Asmedia branded. I say ‘something like’ as the ASM2812 is only publically stated to come in a BGA package whereas that chip is quite clearly QFN. The ASM2812 is also quite conveniently a PCIe x4 upstream to 6x1 downstream switch, and this is an Asrock motherboard.

So, making the assumption that the x1 slots are PCIe Gen 2, a PCIe switch is used and the lowest PCIe slot is shared with M2_2 the inclusion of Thunderbolt isn’t eating any lanes.

I wonder how this would impact IOMMU groups, and when is Asrock going to update their manuals?

5 Likes