Any one here know VHDL or Vivado?

Science, Engineering, & Tech
1

got a project due next friday and I’m trying to figure out
how to set up my code
I’m trying to just build a simple ‘and’ gate in vhdl
and i have no idea were to start with the test bench in vivado
and idea’s?

the boolean equation for this is
a&b=y

this is the code i have so far

task 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;

– Uncomment the following library declaration if instantiating
– any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity task1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end task1;

architecture Behavioral of task1 is

begin

– Enter your code here.
y <= a AND b;
end Behavioral;

and this is the code i have for the test bench

task 1 tb

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

– Uncomment the following library declaration if instantiating
– any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity task1_tb is
– Port ( );
end task1_tb;

architecture Behavioral of task1_tb is

--declaring the component
component task1
    Port (
       a : in STD_LOGIC;
       b : in STD_LOGIC;
       y : out STD_LOGIC);
end component;

--declaring the signals needed
--these a, b, and y signals are different from the
--internal ones of the component
signal a, b, y : std_logic;

--signal to assign values to a and b
signal counter : unsigned(1 downto 0) := "00";

begin
– component assignment
uut: task1 port map(
a => a,
b => b,
y => y
);

    a<= 1;
   b<= 0;
  
  
   tb: process
begin
   wait for 20ns;
   counter <= counter+1;
end process tb;
--assign a (bit 1) and b (bit 0) to the counter bits so that
--all possible inputs are tested
--Enter your code here
   
--increments the counter using a process
--use a 20ns delay between each combination
--Enter your code here

end Behavioral;

any idea’s i’ve tried asking my professor about this but his lips are sealed.

2

You just need to implement an AND gate? The following should work:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity task1_tb is
    Port (
        a : IN STD_LOGIC;
        b : IN STD_LOGIC;
        y : OUT STD_LOGIC
    );
end task1_tb;

architecture Behavioral of task1_tb is
begin
    y <= a AND b;
end Behavioral;

The IEEE.STD_LOGIC library includes an AND implementation, so we can simply declare that y is assigned a AND b.