OK that’s a little confusing to me, I read this: When is 8 memory channels not 8 memory channels? and "It is most correct to say the memory bandwidth doesn’t exactly follow the socket or channels available on the platform, but instead follows the core count. And that (probably) 48 or more cores are needed, because of the # of chiplets involved, to achieve max memory banwidth.
Of course for Epyc, this isn’t so – we have Epyc “F” series CPUs with as little as 1 core per chiplet enabled."
and ChatGPT (fwiw)
Why CCD count does not affect memory bandwidth
On EPYC:
Memory controllers sit on the I/O Die, not on the CCDs.
This means:
- Whether you have 2 CCDs (9115) or 12 CCDs (9754)
- You still have 12 DDR5 channels, each capable of the same MT/s
- Total bandwidth is identical at the same memory speed
Example (your configuration)
You mentioned:
12 DIMMs @ 5600 MT/s
Per-channel (DDR5):
5,600 MT/s × 8 bytes = 44.8 GB/s
So you are saying a different CPU and I’d get better bandwidth?