Nowhere in the manual does it specify that CPU lanes are used for the 2x Thunderbolt 3 ports, and all online material says the TB controller is through the chipset, but a TB controller only uses x4 lanes total, but the lost lanes on a fully populated board exactly matches 2 x4 partitions being sectioned off for the Thunderbolt ports. This doesn’t make sense because the controller only needs x4…
Reviving this topic because Gaming 7 Pro supply is pretty scarce. I haven’t gotten any confirmation about lane assignment on Cascade Lake-X and the X299 Designare EX, so I’m skipping that board.
Anyone have a block diagram for the lanes on the X299 Aorus Master? Which M.2 slots go to the CPU, and which go to the chipset? @wendell of all people should know this since he’s been testing M.2 RAID on X299 the most. Worst comes to worst I’ll pick up a Aorus Master and a few M.2 to PCI-E x1 or x4 risers for my USB 3.0 controllers for VFIO.
I don’t see any info online about the X299 Aorus Master’s M.2 lane assignments.
Well, the X299 Aorus Master manual states that 1 M.2 slot goes to the CPU, and 2 to the chipset. Also that slots “M2P” and “M2Q” share PCIE lanes with SATA ports, which go to the chipset. “M2M” does not share with SATA ports, and is also nearest the CPU.
Strong implication that M2M goes to the CPU. Of course, supporting evidence would be nice to have.
Yeah, and that’s what I’m looking for, supporting evidence.
So, anyone with a 10900X and the X299 Designare EX able to confirm anything on PCI-E layout? I might have to just do this myself if no one has a unique 10900X and X299 Designare EX combo with 3 16x GPUs. My 10920X is on order, and I might have to convince a friend to do a 7900X X299 Designare system just so I can test the theory with enough GPUs.
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