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Xilinx Vivado 2018.3: Implementing my 16-Bit Counter onto the Board


I am currently trying to implement my 16-Bit Counter that I created in Vivado 2018.3 using VHDL to the Nexys 4 DDR board. I already have synthesized the design and ran simulations on the counter and it’s behaving like expected in the simulation but I need to know how I can implement this onto the board.