The reason they cooperated with ARM was linux compatibility and great performance per Watt that was required for the enterprise markets. When they made the deal with ARM they had no CPU alternative to make the Opteron brand competitive. They were pretty much forced to coop with a competitor to not lose market presence completely.
Now though they have EPYC, that is a direct competitor to PowerPCs. It makes no sense for AMD to license the architecture of their direct competitor. For the same reason you will not see Intel on the consortium. These 3 are fighting each other for the market.
If AMD ever gets in the consortium it would only be for their instinct seriesā¦If ever. Providing the Radeon series on Power systems gives an advantage to PowerPCs, an EPYC competitor. They would need a good benefit in return to balanced this out. AMD being in both the GPU and CPU market has much more complex interests on the matter.
RISC-based architectures is not really a family per se. They are ISAs that were designed based on the same common principle of keeping instructions simple and compartmentalized (for example only dedicated instructions can access the memory and no other instruction). From there you can design whatever you want yourself based on this principle.
RISC is a design concept. RISC-V is a specific ISA designed using the concept. Power ISA is another one. They do not really have any relation to each other besides this.
This might be news to most but to those that studied computer science itās an open secret. That ever since the Pentium Pro and K5, X86 has been a RISC architecture.
X86 simply places a very advanced opcode decoder abstraction(along with a different way of memory access) in front of the internal functioning of a CPU.
Internally these X86 instructions are decoded into Micro Operations (uops) that are executed by the various RISC substructures, legacy X86 circuits and ASICās.
Well, sort of. There was an distinct Berkeley RISC architecture, which SPARC, MIPS, ARM, AMDās Am29000, and Intelās i960 are descended from, which was more than just a concept. POWER though, traces back to IBM 801 which had no influence on Berkeley RISC.
That is what I was talking about in the post you replied to; the K5 core was Am29000 which was a descendant of Berkeley RISC, while POWER was a descendant of the IBM 801 design. Since AMD has used Berkeley-style RISC designs in the past, it makes sense that they might have more interest in RISC-V then an IBM 801-based design. Then again, Iām just guessing here, maybe by now POWER and architectures descended from Berkeley arenāt so different at all.
Yeahā¦ I read the āgoogle is your friendā and overreacted a bit. Sorry on my end as well.
I have experienced the ājust go google itā response on other forums, and mistakenly assumed before calmer thoughts prevailed.