The real issue is that they did the “gen” naming prefixed by “3.1” and “3.2”; if they had just left it at generations of USB “3”, and banned the possibility of “gen 1x2”, I think that would have been fine,
3.0
3 gen 1
SuperSpeed5
3.1
3 gen 2
SuperSpeed10
3.2
3 gen 2x2
SuperSpeed20
Then it would not be possible to disguise a 3.0 port as 3.1 or 3.2. As it is currently, 3.1 and 3.2 are meaningless because:
Reality
marketing
3.0 = 3.1 gen 1 = 3.2 gen 1
SuperSpeed
3.1 gen 2 = 3.2 gen 2 ≈ 3.2 gen 1x2
SuperSpeed+ 10Gbps
3.2 gen 2x2
SuperSpeed+ 20Gbps
According to the usage guidelines, the plus designation is “not intended to be used in product names, messaging …” but that ship sailed when they added the + to the logo for 10Gbps and 20Gbps.
The x2 actually is not that bad in my opinion, since it basically tells you whether or not you need a type C connector for that speed, since only type C can provide two lanes.
However, I have yet to hear a compelling reason for defining 3.2 gen 1x2 at all; it creates is a possibility where some 10Gbps devices operate at max speed on a type A port, where others will run at half speed unless on a type C port.
The x2 refers to making use of the additional of Superspeed RX & TX conductors in the Type C connector:
Type A: RX−, RX+, TX−, TX+
Type C: RX1-, RX1+, TX1-, TX1+, RX2-, RX2+, TX2-, TX2+
It sounds like originally these were there for the reversibility, but 3.2 defines repurposing them as an additional lane for gen 1 (5 Gbps) or gen 2 (10Gbps) traffic.
There are also duplicate USB 2.0 lines in the Type C connection, so perhaps we should count ourselves fortunate that we are not also dealing with a USB 3.2 v2.0x2 standard at 960 Mbps!
Maybe that could have been USB 3.2 gen 0?
USB 2.0 (480 Mbps) → USB 3.2 gen 0
!NEW¡ (960 Mbps) → USB 3.2 gen 0x2
I recall that 3.2 gen2 x2 was supposed to use more lanes to double the transfer. It technically isn’t Universal Serial Bus now anymore, because it has 2 lanes, so it would be Universal Parallel Bus. I really want that job.
Universal Dual Serial Bus my friend, let the professionals handle this
Joking aside, I think that would technically be correct, parallel bussing would mean that all four differential pairs are synchronised and share the same clock, no?
Actually, if the differential pairs are clocked independently (which I am not positive they are), maybe you could clock them at different speeds, and create a monstrosity like gen 1+ 2, transmitting at 15 Gbps, or for greater insanity, even set different up/down speeds:
USB 3.2 gen 1+2 up/ gen 2x2 down
I assume the USB controller might crash out if you actually tried to do that.
