Trying to Predict the rest of the Ryzen 5000 Product stack with info we know!

[Kamen_Rider_Blade]

So given the information we know about the existing Ryzen 5000 series CPU product stack, I’m going to try to predict the future with some educated guesses.

Here’s my current forecast / prediction into the future

Take everything I predict with a grain of salt.

The one thing that strikes me is that Zen 3 will eventually need a 4-Core CCX part to cover their bottom end of the product stack.

Do you think that they’ll just update the existing Zen 2 4-Core CCX die and update it to Zen 3 and leave out 16 MB of L3 cache and call it a day?

I think that’s incredibly plausible since it would require the least amount of work.

If they were to make a new 4-Core CCX with 32 MB of L3 cache, what would it’s die layout look like?

My prediction for what it would look like is this.

That’s a chicken scratch version, there would be a Double Direction Ring Bus linking to each chunk of 512 KiB L3 cluster that can be shared amongst all 4-core CCX’s. The center white area between Cores would be some sort of Infinity Fabric link/Switch that can filter around data between the 4-Cores and the L3 Cache clusters on the RingBus. The advantage to placing the 4 cores right next to each other is latency between the 4 cores should be far less due to distance. The disadvantage is L3 latency will vary depending on how far away data is and how long it will take to propagate to L2 via the Central Switch.

But that’s just me thinking up of a unique solution to a problem that might happen.

Realistically, I think they would update the Zen 2 4-Core CCX and just omit the extra 16 MB of cache and call it a day. Slap those 4-Core CCX into the bottom tiers & mix and match based on binning of defective cores.
That requires the least amount of effort to the existing manufacturing process.

@wendell what do you think about the future of the Ryzen 5000 product stack with the information you know.

Any fun guesses as to what the product stack might look like?

Anybody else want to take a serious stab at guessing the future of Zen 3 Ryzen 5000 product stack?

[DarkIce83]

will there be any APUs on 5000?

[merry]

If a 4 core Zen 3 ever exists it’ll be because they’ve stockpiled chiplets that fail to bin as anything better. On Zen 2 all other things equal that was much more likely because of the split layout, even then it took a long time to have enough to release a product and the supply of them evaporated quickly. If I was a betting persion I’d say that a Zen 3 quad core would be OEM-only if it ever exists.

[Whipple_Jaeger]

I am conflicted with the Zen2 (XT) launch this past summer. Were they designed as such? Or remnants of Zen2 processors for the processors in the consoles and AMD repurposed them for desktop usage? (As I do not recall an Epyc release based on those 7nm presses).

If it were a planned release, why waste the 7nm wafers and capacity for cpu “refresh” yet again? When it could have been better used on the Zen3 or RDNA2 launch. I fail to see its intentions, my concern as a user is whether to purchase a 5900x once readily available or expect another “release” of an 5900XT later down the road.

Currently, I’m using x570 platform with a 2700x, and have a b450m motherboard to transplant the cpu onto assuming Zen3 is readily available and somewhat discounted. Just would be uneasy with more untimely shenanigans.

Speaking on topic with product stack: Do Athlon chips ever see Zen 3 utilization? I’m certain they can be refined, but then what of mobiles chips? Too many choices for AMD to make, and their low end spec market is not (nor should be) a priority at this time.

[merry]

As a process node matures yields and bins tend to improve, AMD decided to create a slightly refined line to make use of the better bins. They could do the same with the 5000 series, but the process may not mature too much from now so maybe not. If they do a 5000 series XT I bet it’ll be to say they can hit 5GHz boost OOTB.

[SapphironZA]

I suspect that yields are good enough on 7nm that they don’t really have enough 4core CCXs for a retail product.

They will likely go into industrial applications and OEMs as suggested.

I think Ryzen entry level wil continue to use global foundries zen+ dies for the next few years. At least until they transition to 5nm. The 1600 af is still a great productivity CPU

[Kamen_Rider_Blade]

Now that a real Zen 3 Die shot is out, I can make a newer guess as to what I think the 4-core CCX Die would look like.

This is the actual Zen 3 Die with labeling:

This is my new prediction for the 4-core CCX Die with newer data:

So the main difference is that extra L3 sitting in between the individual Zen 3 Cores.
Those would be converted to 2 MiB of Private L3 $ per core and the extra logic to back that would be added as needed.

This would offer some performance improvements while the main Shared L3 $ is a bit smaller at 24 MiB for 4-cores.

So TLDR: the major change is:

• Shared L3 $ = 24 MiB
• Private L3 $ = _2 MiB/core

What do you think now that we have newer data to work with?

[merry]

Is there precedent for multiple types of L3 cache used simultaneously? I think if cache is to be messed with that increasing L2 cache would be a more natural step, but more likely there’ll be no cache changes at all in a hypothetical quad core. The benefit to spinning a quad core part would be the smaller die size so they can be pumped out economically.

You know what would be really cool? A 7nm die containing cores, large L1 and large L2, stacked on top of multiple dies from an older node dedicated to a massive amount of L3.

[GoldenAngel1997]

I’d doubt they bring back odd core variants, harkening back to Phenom times

Anything on deck, maybe would be the non-X skus [5600, 5800, 5900] [lower silicon lottery, like reduced boost ceiling]. I’d anticipate an APU [5400G] in '2021, but question be would they rehash Vega once more… or this be debut of RDNA-embedding?

[Kamen_Rider_Blade]

@merry

Is there precedent for multiple types of L3 cache used simultaneously? I think if cache is to be messed with that increasing L2 cache would be a more natural step, but more likely there’ll be no cache changes at all in a hypothetical quad core. The benefit to spinning a quad core part would be the smaller die size so they can be pumped out economically.

You know what would be really cool? A 7nm die containing cores, large L1 and large L2, stacked on top of multiple dies from an older node dedicated to a massive amount of L3.

All that sounds like big 5nm changes that would be done on Zen 4 vs working with existing architecture in Zen 3 and the existing IO Die.

[Kamen_Rider_Blade]

@GoldenAngel1997

I’d doubt they bring back odd core variants, harkening back to Phenom times

Anything on deck, maybe would be the non-X skus [5600, 5800, 5900] [lower silicon lottery, like reduced boost ceiling]. I’d anticipate an APU [5400G] in '2021, but question be would they rehash Vega once more… or this be debut of RDNA-embedding?

Given modern binning where they can turn On/Off individual cores, there has to be some minimum level of yields for each 8-Core CCX/CCD and 4-Core CCX/CCD.

With modern 7nm that is mature and proven, you have 8-Core CCX/CCD with yields of good 8/7/6/5 cores realistically.

4-Core CCX/CCD would be down to yields of 4/3/2 cores given how mature the process is by this point.

Now you can mix & match as you feel to make a product tier.

[merry]

Yeah, I went off on a tangent. For the existing arch I go back to them not wanting to tape out a new design without good reason, the only one that makes sense for a low tier part like a quad core would be to save die space IMO. OEM’s would love it but that’s about it.

As another tangent, for a similar reason I’m surprised at the 5700u (and odd 2nd digit company) rumors of being updated Zen 2 with more cache, as that should require a new taping which is a curious choice for an old design. The only logical reason I can see for that would be if the Zen 3 APU’s will be on an updated process and AMD want to maintain an updated design on the older process to keep output maximized even as Zen 2 desktop demand starts dwindling.

[GoldenAngel1997]

With the chiplet implementation, their be near-0 worry of followup work / nerfing down an assembled processor, just to find an [unnecessary] sku opportunity. Phenom AM2+/AM3 did this, with their X3 / some X4 chips, when 1/2 core was poor performing or vegetative [native 4c / 6c design], to still find an audience and reduce wasted chips… these block core(s) could be unlocked, by the user should they desire [with risks taken knowingly]