Hi,
I wanted to build a very low power virtual hosting box for personal testing. So i grabbed a board that has a 10W CPU
and installed linux on it and i have a number of devices on it how ever theres one kink in my plans that has me scraching my head. I suspect that the threads are not enabled
The celeron cpu (J3455 ) and im running centos7 with 4.9.0-1 kernel and hyperthreading enabled in the bios.
Am i missing some thing or should I forget the output of lscpu ?
If theres a forum/place thats better for looking for this kind of stuff please drop a link.
lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 92
Model name: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
Stepping: 9
CPU MHz: 1004.333
BogoMIPS: 3005.40
Virtualization: VT-x
L1d cache: 24K
L1i cache: 32K
L2 cache: 1024K
NUMA node0 CPU(s): 0-3
dmidecode -t processor
dmidecode 3.0
Getting SMBIOS data from sysfs.
SMBIOS 3.0.0 present.
Handle 0x0015, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPUSocket
Type: Central Processor
Family: Celeron
Manufacturer: Intel
ID: C9 06 05 00 FF FB EB BF
Signature: Type 0, Family 6, Model 92, Stepping 9
Flags:
FPU (Floating-point unit on-chip)
VME (Virtual mode extension)
DE (Debugging extension)
PSE (Page size extension)
TSC (Time stamp counter)
MSR (Model specific registers)
PAE (Physical address extension)
MCE (Machine check exception)
CX8 (CMPXCHG8 instruction supported)
APIC (On-chip APIC hardware supported)
SEP (Fast system call)
MTRR (Memory type range registers)
PGE (Page global enable)
MCA (Machine check architecture)
CMOV (Conditional move instruction supported)
PAT (Page attribute table)
PSE-36 (36-bit page size extension)
CLFSH (CLFLUSH instruction supported)
DS (Debug store)
ACPI (ACPI supported)
MMX (MMX technology supported)
FXSR (FXSAVE and FXSTOR instructions supported)
SSE (Streaming SIMD extensions)
SSE2 (Streaming SIMD extensions 2)
SS (Self-snoop)
HTT (Multi-threading)
TM (Thermal monitor supported)
PBE (Pending break enabled)
Version: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
Voltage: 1.2 V
External Clock: 100 MHz
Max Speed: 2416 MHz
Current Speed: 1500 MHz
Status: Populated, Enabled
Upgrade: Other
L1 Cache Handle: 0x0013
L2 Cache Handle: 0x0014
L3 Cache Handle: Not Provided
Serial Number: Not Specified
Asset Tag: Fill By OEM
Part Number: Fill By OEM
Core Count: 4
Core Enabled: 4
Thread Count: 4
Characteristics:
64-bit capable