High quality, soldered construction as expected. No mayonnaise here.
What is surprising is that it is actually 4 dies. So just Epyc with two turned off. I had assumed it was just two.
Interesting… And also makes it very easy for AMD to quickly respond to that 18 core Skylake chip if it ever becomes an actual thing…
Assuming the socket pinout is the same as EPYC and so on I don’t see any reason for why AMD couldn’t use more than two dies for threadripper.
They could on theory launch 32 core threadripper parts, but the pci-e IO on threadripper is still limited to 64.
I think all of the threadripper parts have the same dies disabled, because the pci-e IO pads underneath the CPU that are used for the pci-e slots are the same.
AMD claiming it is only using two dies of the four does not make logical sense now that the chip has been delidded. I can understand that they want to differentiate it from Epyc though
It would make more sense, given the cooling challenges that the 180W TDP chips will have to deal with, to use a ccx module with four cores in each die and spread smaller localized areas of heat over a wider area of the heat spreader.
there would be no additional performance penalty spreading the modules between all four dies. Dual socket Epyc only shows extra latency when switching between sockets, not between ccx modules in the four dies on chip.
So that is where AMD is hiding the dead bodies. xD
From what I have heard a few times, but have no ready source, is that is is not 2 Core CompleXs turned off from epyc but that the 4 CCXs are running but with only 4 cores in each CCX enabled.
Makes sense with AMD maximising yields two fold. Many CCXs with many cores so less reliance on getting single monolithic chips working, and then if some of those smaller CCXs have defects you turn off those individual cores. So more yelids for the CCXs, lower heat out put from each distributed over a wider area.
It is all smart stuff coming up AMD.
EDIT: This is interesting, I have been watching the video and he reiterates the same 2 CCX thing, which I had never heard before (only heard 4 cores in 4 CCXs), saying that AMD has said this and the said it again when they asked after the delidding. I will have to try keep a look out for the information I had seen about the 4/4 layout, it seems odd that is is 8/2 when the are 4 CCXs on there.
I will say that people claimed it would be impossible to have the 6 core 1600s configured in a 3c per CCX and that it would have to to be 4c in one and 2 in another. This apparently came form some wizard class overclocker. Will lo and behold it was 3c per CCX. SOOOOOooooo I do no trust any one saying is is 2 8cores CCXs with out proof other than in word.
I wonder if it will come to light eventually that some are 2 CCX 8cores and other are 4 CCX 4cores and others further for the 12 core ones could be, 3 CCX with 3 cores.
I always heard it was 2X8 Zepplin dies. I had assumed that was all that was on there. Not 4. That made sense to me because that is the easiest way to half the number of PCIE lanes and memory channels. Plus more dies always increases latency or introduces other issues.
I’m assuming this is just cheaper to make since they don’t need another interposer design. Yields are so high it really doesn’t matter. Plus allows them more freedom if we see a higher core count.
AMD has said the twelve core is 2x6
A few things to note, if there is in fact 4 dies that are turned on it would make it an 8 channel memory system instead of 4.
Another thing to note is that there is 64 pci-e lanes, EPYC has 32 in each die, hence 128 lanes.
It makes more sense cache wise to use 2 dies instead of 4 with half of it disabled, higher cache sizes per die decreases latency compared to having the l3 spread across 4 dies.
AMD have been saying that Threadripper is two dies which in functional terms it is. In physical terms we discovered today that Epyc and Threadripper come off the same production line. Being modular AMD can just disable whatever CPU cores, memory controllers and pcie lanes that they want to.
Having to only use 1/2 the available CCX modules to make a 1950X and 1920X chipx very flexible for AMD to manufacture picking up the reject Epyc chips where either one CCX modules is faulty or one of the silicon dies is faulty, The can reconfigure the CCX and controllers and sell it as as a Threadripper. It is a byproduct of Epyc production just as R5 and R3s are byproducts of R7 production.
The architecture that AMD is totally different conceptually than what Intel has been doing. Don’t fall into the trap of thinking the chip is “glued together”. It isn’t. The infinity fabric actually makes up the foundation of the processor, not the silicon rectangles. Those rectangles that you see are not dies in the traditional Intel sense conceptually speaking, they are effectively just scaffolding that holds the CPU and controller modules in place and those modules connect directly to the underlying Infinity fabric to communicate anywhere on the chip.
While there is a difference in latency switching a thread between two cores on the current CCX and switching to another CCX module. The latency stays the same regardless of what CCX it switched to on the Chip, regardless of what silicon die it exists on. The thread data runs down the interconnect from the originating CCX to the fabric and then across the fabric to any other CCX module on the chip, regardless of whay die it resides on, then up the interconnect.
The next step up in latency only happens in dual socket Epyc servers if a thread tries to switch between sockets. But that is the same for both AMD and Intel.
Each CCX module has its own 8MB L3 cache and that is fixed. Two CCX modules on a single die as used in the R7, gives you the 16MB in total L3 Cache
The INfinity fabric means It makes no difference where the CCX resides on those chips.
MB…
Doh. of course you are right. I fixed it
This processor looks incredible. I can’t wait to get my hands on one. I’m sort of planning a high end workstation build based on Threadripper. The four individual dies looks really cool. Maybe it’ll be something similar to how you could roll the dice and unlock Athlon II X3 CPU’s to either X4’s or Phenoms.
Strange that the video was taken down at AMD’s request. I was thinking that the whole quad die setup was something they might not have wanted out there. At least not yet. If each die is 8-core, that means they are probably planning a monster 32-core, 64-thread SKU.
AMD claim that 2 of the dies are only dummies, I am not sure that I believe that. I can understand AMD not wanting people trying to hack the chips to enable extra cores.
On the other hand, if their production methods were perfect, There would be no R5 and r3 chips on the market. Threadripper makes those partially defective dies much more profitable than selling them packaged up in an r5 1400 or 1500x chip.
The MB socket pinouts are different between x399 and the server boards, at least with the ASUS zenith boards, so it is possible that even if you could enable the extra cores, you have no way to access them.
CPU looks great thus far; I have no complaints. Intel has been known to do shadier things in the past.
I asked for what is essentially threadripper a few years ago, a huge SOC that makes 2011 look small and has tons of stuff.
TR has tons of stuff, huge package.
My.body.is.ready
This is amazing. I just thought of this, but x86 in the consumer space is finally doind what arm did an eternity ago.
There was some discussion on the LTT forums as to whether or not two of the dies are just “dummy dies”, there simply to prevent the heat spreader from flexing or caving in when a cooling solution is applied.
No idea if that is the case or not.
I read somewhere that two of the cores have been turned off… I wonder hmmm ;p
That’s what PC Mag and apparently what AMD said to him…
I mean it honestly would make sense. They are using the same interposer because it’s cheaper but they’d need something to support the lid…
I really don’t think they’d waste good dies. Even if yields are perfect throwing away two working dies seems an odd choice