I think that the Kabylake X chips have been released as place fillers so that the Intel can start selling Coffee Lake mainstream and Coffee Lake X HEDT cpus at the same time without having the appearance of a skipped generation of HEDT CPUs.
I also don’t think the 28 vs 44 PCIe lanes is an artificial segmentation. It is because of a limitation of the architecture that Intel has moved to.
The new Skylake-X CPUs are being built in a grid layout as opposed to the older Ring design. The CPUs with up to 8 cores I think are built on a 4x4 grid and the 10 core and above CPUs are being built on a 6x6 grid. The PCIe parts of the die occupy one edge of the square grid. Two of the grids are dual channel memory controllers and the rest are either allocated to the CPU cores or are disabled. Designing in disabled grid spaces would help with yields and I am guessing temperatures.
Each of the grids for PCIe can host x8 Pcie lanes. the 4x4 grid allows for a maximum of 32 lanes. 4 of the lanes are allocated to DMI/chipset leaving 28 Lanes remaining to the motherboard slots. The Layout for the i7 Skylake X chips being something like this with P for Pcie, C for Core, B for Blank and M for memory controller
P P P P
C B C M
M C B C
C C C C
The i9 branded chips are built on a die with I think, a 6x6 grid. The 6 Grid spaces for IO give them the possibility to do 48 PCIe lanes with 4 going to DMI/chipset and the remaining 44 available for the user.
I think that the i9 chips are something like this for the 18 core variant. Obviously add more Blank grid spaces for the lesser cored versions. Spreading the blank grids helps spread the heat load over a wider area of silicon
P P P P P P
C C B C B C
M B C B C C
C B C B C M
C C B C B C
C B C C B C