The RYZEN 1000 Thread! Summit Ridge - General Discussion

Apparently Geekbench has a bug in detecting correct L3 cache size.

It calculates the total L3 size and then still appends the multiplier.

https://browser.geekbench.com/v4/cpu/2522347

So L3 cache size is no longer a useful indicator as above.

1 Like

Realized that I dont understand whats L1,2,3 caches doing, so…

L3 cache is shared between all cores
L2 cache is shared between two cores
and every core has its own L1 cache

Did I figure it right?

Ryzen 7 (8 Core)

Cache Size Associativity
L1 Instruction Cache 64 KiB/core 4-way set associative
L1 Data Cache 32 KiB/core 8-way set associative
L2 Cache 512 KiB/core 8-way set associative
L3 Cache 2 MiB/core 16-way set associative

In a 6core Ryzen 1600 for example you would actually have 2730KB L3$/core. But the L3 cache is shared so you can’t purely tie it to just specific cores :wink:

Thats the very simple version of it.
I’ll write More about it some later point.

You should read the CPU cache wiki if you want to learn more.

1 Like

OC’ing
on a stock cooler…promises a better article to come later

i was able to get a stable 3.9ghz on the 2400g , but it ran to hot for comfort. so i would need a better cooling solution to run at that clock .

1 Like
2 Likes

How many of that voltage did it want, and for my 1700 at least that tighter LLC setting has been doing better heat wise

Did you use Ryzen Master or the Bios.
They never came out with a Kavari master ::sob:

i just bumped the multiplier up in bios. didnt change the voltage, according to some i could even drop the voltage ,even after bumping the multiplier up.

bios. because , eh why not?

1 Like

Finally got around to BIOS updates on my Asrock AB350M Pro4. Now on BIOS P4.50.
R7 1700 P-state overclocked to 3.75 @ 1.1875V (there’s no voltage offset option, so nothing higher on P-state 0). May go for a 24/7 overclock to see how high I can push it. There’s also no LLC, so when system is balls to the wall I get about 60mV droop to 1.125V.

More importantly getting on AGESA 10.0.0.6b finally got my RAM to 3200. Corsair LPX (CMK16GX4M2B3200C16W) @ 16-18-18-18-36-**. I was stuck at an unstable 2666 before so just ran it at 2133 for stability. That’s with 1.35V and no SOC or VDDP changes.

Well, not exactly those numbers…my base clock is 99.8 MHz rather than 100 :stuck_out_tongue:

edit: ** used to show 54 but apparently I typed 54 into a field that was meant for hexadecimal so I was running 16-18-18-18-36-84 :flushed: Still need to see how low I can get tRC. 54 was unstable.

Just saying because some like to do these insane day long stability grinds

I’m fine with that 1 hour prime95, where it changes that new style and temp jumps another 1-2C
It seems to be 24/7 stable, and sort of similar to converting videos

Managed to get 3600 CL16 to run, BUT the damn thing crashes every time to geekbench 60%~ AES part so that cursor and view freezes, voltage is not the issue because its the same from like 1.375 to 1.5, SoC is doing the same from 1.15-1.2

I must be missing something else

Cryptography Workloads
AES
The Advanced Encryption Standard (AES) defines a symmetric block encryption
algorithm. AES encryption is
widely used to secure communication channels (e.g.,
HTTPS) and to secure information (e.g., storage encryption, device encryption).
The AES workload in Geekbench 4 encrypts a 32MB string using AES running in CTR
mode with a 256-bit key. Geekbench will use AES instructions when available
, and fall
back to software implementations otherwise.
Devices with superior AES performance can have a noticeable effect on the usability of
the device. See, e.g.,http://arstechnica.com/gadgets/2015/03/review-the-new-moto-e-is-the-most-phone-you-can-get-for-150/3/

3200 cl12 crapped itself way worse with identical voltage, and some software things did not start at all

@SgtAwesomesauce and @Steinwerks, lets bring that over here.

The memory channel stuff is one thing, then there is registered support, number of cores, PCIe lanes and not to mention dual CPU config. Honestly, running Epyc in a TR4 board doesn’t make sense. But I would love to see an Asus Epyc WS board.

1 Like

Have you tried slightly increasing VDDP?
Try to go up towards 1.0V. Don’t hammer SoC too much.

1 Like

It’s also not electrically(physically) possible.

Check the CPU MCP (Multi Chip Package)

AMD Threadripper

https://en.wikichip.org/w/images/c/c1/AMD_Threadripper_SoC.svg

Core config

https://en.wikichip.org/w/images/d/d3/zen_soc_block_(16_cores).svg

AMD Epyc

https://en.wikichip.org/w/images/3/39/AMD_Naples_SoC.svg

Core Config

https://en.wikichip.org/w/images/d/d5/zen_soc_block_(32_cores).svg

Note all of the extra Memory Channels and GMI’s(Global Memory Interconnect’s) on the SDF.

You can’t even bootstrap the system with those being connected to un-powered dies (Mainboard limitation).

And if by some 1337 h4x0r magic you did manage to boot Epyc on TR4 X399, you would then be stuck with half the GMI bandwidth compared to Threadripper (1x 39.74GB/s vs 2x 95.2GB/s and the same 16 cores compared as a 1950x.

Why? Because the MCP is physically wired that way and Epyc is not built for X399 which isn’t wired to power Epyc MCP’s.

So you have nothing to gain and more to loose.

Simply Googling “VDDP ryzen” already shows your answer as first answer

So, 1,5 dram, 1,2 SoC, 1.0 VDDP

:sparkler::fireworks::sparkler::fireworks:
explosions
:fireworks::sparkler::fireworks::sparkler:

I know that one tick up from 1.5 ram doesnt go well, and havent had reason to rise over 1.15 SoC

I would take SoC voltage as low as possible.
It’s power draw goes mental with higher voltages and I suspect it really can’t take it long term.

To be seen where I organize that VDDP, but as I noted you sometime ago, that 1.143 SoC did correct odd tCWL behavior, and lower stable ram voltage like tick or two

Kinda have to do it

  1. VDDP
  2. ram
  3. SoC

https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram

TLDR: It’s very finicky.
VDDP is basically the Ram Mood adjustment knob.

2 Likes