The POWER and PowerPC General Discussion / News Thread

PPC will never replace mobile. It is too power hungry to enter that market without Architecture fragmentation. RiscV will more than likely unseat ARM before PPC gets there.

On the other hand, AMD had given the PPC architecture a run for it’s money in the enterprise world. PPc only holds a small, but well deserved, niche in the enterprise environment. POWER is working on that now and Power9 was the first major step in that direction.

Where OpenPOWER can clean house right now is to convert the aging MIPS market since MIPS is pretty much dead at this point. And have Oracle license POWER to replace SPARC since Toshiba is never going to release the new SPARC processors it has been working on for the last 7 years or so.

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Welp.

I guess you missed discussion in the lounge about my college days xD

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Mips mean nothing today

Processor throughput means something

Yeah. As a RISC fan in general, MIPS always fit the bill when power usage was the limiting factor. Then ARM ate most of that market except for the few niche cases. Then PPC cores on smaller dies ate most of the other MIPS market (routers and logic systems) and most embedded use cases.

MIPS could win some of that back if actually release 64bit MIPS but between all of the passing around that has happen to the MIPS company, it is basically vapor ware at this point.

Also I don’t mean Millions of Instructions Per Second, I mean Micro Processor without Interlocking Pipeline Stages. The RISC architecture that eventually influenced the ALPHA architecture.

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https://www.anandtech.com/show/15967/nuvia-phoenix-targets-50-st-performance-over-zen-2-for-only-33-power

Now Nuvia wants to enter the ARM Server market.

Within the Enterprise RISC world, do you think ARM Server’s will eat Open POWER’s cake or can they co-exist?

https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor

Marvell has the ThunderX3 with 96C/384T on TSMC 7nm.

That’s worth keeping an eye on.

https://www.anandtech.com/show/15575/amperes-altra-80-core-n1-soc-for-hyperscalers-against-rome-and-xeon

Ampere Altra has 80C but Single Threaded for security.

How is POWER10 looking?

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POWER10 is on the schedule for Hot Chips 32 day 1 of talks (2020-08-17), so in a week we will have more information. Anandtech has an article about the schedule.

Officially

Besides that, the most recent article specifically about POWER10 is probably,

Though there is ongoing work to add support to the linux kernel, phoronix usually mentions this:
https://www.phoronix.com/scan.php?page=search&q=POWER10
most recent article at time of posting is about changes in Linux 5.9:
https://www.phoronix.com/scan.php?page=news_item&px=Linux-5.9-More-POWER

Unofficially Confirmed via Twitter

in the comments for a recent Talospace post, Raptor said:

There will probably be some exciting announcements for POWER hardware late this year / early next. Not POWER10 yet (IBM made some very poor choices regarding POWER10 that currently block our products and that we continue to work to resolve) but POWER overall is looking quite healthy for the future. For now, POWER9 is definitely the best way to go to get an open, owner-controlled, powerful system with long term support and tons of distro choices!

Not yet. We’re keeping it a bit under wraps at the moment while negotiations etc. are carried out, but suffice it to say any POWER10 systems from competitors in the interim will not meet the normal Raptor standards due to the causative IBM decisions.

Edit:

Other assorted news

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Hot Chips 32 POWER10 Info

Courtesy of Ian Cutress (Anandtech):
Hot Chips 2020 Live Blog: IBM’s POWER10 Processor on Samsung 7nm (10:00am PT)

  • 602 mm² on Samsung 7nm node
  • die is physically 16 SMT8 or 64 SMT4 cores, though one core (or core pair for SMT4) is disabled for yield reasons - in practice this is what happened with POWER9 anyway, most cores per
  • on-track to deliver systems in 12 months
  • 3× efficiency relative to POWER9
  • 10-20× matrix-math performance per socket relative to POWER9
  • 2× “general” SIMD and 4× matrix SIMD per core relative to POWER9
  • chip connected to the outside world via PCIe 5, OMI, and PowerAXON (OpenCAPI, NVLink, processor interconnect, etc.)
    • OMI (Open Memory Interface) takes the place of a direct DDR4 or DDR5 connection
  • will be available as either:
    • SCM (Single Chip Module) - up to 16 sockets
      • up to 15 SMT8 (30 SMT4) cores
      • 4+ GHz
      • 32 lanes of PCIe 5
    • DCM (Dual Chip Module) - up to 4 sockets
      • up to 30 SMT8 (60 SMT4) cores
      • 3.5+ GHz
      • 64 lanes of PCIe 5
  • PowerAXON and OMI support 1TB/sec each
  • Memory Inception appears to be a feature to allow multiple machines to share RAM over a local network with minimal overhead

I think the benefit of the OMI interface replacing direct attached memory (DDR_) is that while it is said to add < 10 ns of latency, it greatly increases the possible memory bandwidth. It will also allow the same CPU to upgrade from DDR4 to DDR5 memory; however, this requires special DIMMs with an OMI controller. It may be possible to have an OMI controller on the mainboard, and use standard memory (Raptor was planning to do this for Talos I, as POWER8 used the predecessor Centaur memory interface) but then the board could only be compatible with either DDR4 or DDR5.

See also

Patrick Kennedy (ServeTheHome)


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I’m guessing this is for blade servers or something similar. But still, wew.

surprised pikachu face
Wouldn’t this mean POWER10 would basically beat AMD in performance / watt? Things are getting exciting. Gotta read the article…

Probably not, IBM has been doing this for a while, each set of four sockets is rack mounted separately in (I think) 4U. Then there is also a 1U controller unit. If you are curious look up E_80 (E980 for POWER9, E880 for POWER8).

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^This.

I do wonder about power efficiency since that has never been an attraction factor for Power/PPC. But if they are able to at least get down to EPYC levels of power efficiency, we may just have a real architecture war in the enterprise world with x86_64, Aarch64, and Power.

Toshiba, when are we ever going to see the new SPARC?

All the benchmarks that I’ve seen for SMT8’s performance boost over SMT4 is relatively minimal.

Would a nice compromise be SMT6 theoretically?

And man, this years reveals has some ridiculous Cache architectures and CPU architectures.

Thunder X2 has 32 MB L3
Thunder X3 has 90 MB L3

Thunder X3 also has 64 KB L1 I$, 32 KB L1 D$ which is kind of odd to be that mismatched.

512 KB L2 $


The ThunderX3’s architecture is “Unique” to say the least.

POWER 10:
120 MB L3 <- EPYC size L3 cache going on!
2 MB L2 per core <- That’s 4x the size of Zen 2’s L2
48 KB L1 I$, 32 KB L1D$ <- Interesting choice compared to it’s RISC ARM based cousin

The Architecture looks intriguing

OMI’s flexibility sounds AWESOME, I wish consumer platforms could get access to it.

The Memory Inception looks AWESOME in terms of functionality.

The IBM z15 also looks neat as that other CISC based cousin.
z15:
960 MB L4 cache <- @@ OMG, OverKill, I love it!!!
128 KB L1 I$, 128 KB L1D$ <- That’s HUGE
L2 I/D$ (4MB) Private <- Interesting choice to divide it to I/D sets
256 MB L3 <-@
@
5.2 GHz Frequency!!

:frowning:
Screenshot_2020-08-18 Raptor Computing Sys ( RaptorCompSys) Twitter

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Oooof.

https://www.anandtech.com/show/16007/hot-chips-2020-live-blog-manticore-4096core-riscv-330pm-pt

Manticore 4096 core RISC-V CPU using older 22mm FDX process @ GloFo beating out more modern CPU’s.

RISC-V is Blowing my mind with these kind of announcements + POWER10.

Were I to guess, I think it might be either an initial lack of low end part for POWER10 (Sforza being this for POWER9), or the mandatory use of OMI, that Raptor is disappointed about.

EDIT: While the above may be a concern, there is credible (in my opinion) suspicion that Raptor may in fact be concerned about part of the firmware stack being closed-source, or in some other way not owner-controllable. If you only wish to read the original post about OMI, please skip to the “Options for implementing OMI” heading.

Talospace and Phoronix suspect that IBM may be requiring some firmware blobs (at least initially) to remain closed-source:

Phoronix
Libre/Open-Source POWER10 Hardware Systems Unlikely Until At Least 2022

While Raptor Computing Systems has been making fabulous 100% open-source/libre hardware systems based around POWER9 with the likes of their Talos II and Blackbird systems, don’t hold your breath on quickly seeing fully-open POWER10 systems…

This does seem to better explain the rather harsh comments that Raptor made about IBM “blocking” their products, and that “POWER10 systems from competitors in the interim will not meet the normal Raptor standards due to the causative IBM decisions”.

If we want to be optimistic about the way Raptor talks about the “interim”, I have some speculation: For POWER9, IBM presents itself as having entirely separate firmware for its PowerVM systems (IBM i, AIX, Linux on PowerVM). Maybe IBM is holding back the OpenPOWER firmware until 2022, because the only machines shipping in 2021 will be those running PowerVM.


The following is the rest of the post as originally written:

Options for implementing OMI

To detail the OMI issue, as I see it, POWER10 board vendors have three options:

OMI Option A - OMI modules

This is akin to how all IBM POWER8, and some IBM POWER9 machines attached memory; IBM would manufacture custom “CDIMMs”, modules with memory chips and Centaur memory-controller/buffer/L4-cache. An article by Johan de Gelas (Anandtech) has photos and diagrams of this.

With POWER10 and OMI, this is less of a proprietary solution, and I believe Micron has said they will make these modules. Using OMI memory modules directly would make the switchover from DDR4 to DDR5 very simple, just buy newer OMI modules; however, unless other widely used architectures (ARM, x86) also adopt this, these modules might not see similar economies of scale, or even if the POWER10 market can drive the necessary volume, resellers of OMI memory may be hard to come by, and less willing to deal with individual end-users.

OMI Option B - on-board controller, DDR4/DDR5 modules

As I mentioned in the Hot Chips 32 post, if you look at Raptor’s proposal for the POWER8 Talos I, they planned to use normal DDR3 DIMMs by moving the required Centaur chips onto their mainboard, which I imagine adds expense, complexity, and consumes board space. Looking at the Talos I design, these were probably under the two rectangular heatsinks between the DIMM slots:

Talos I diagram legend
A. 1 × PCI slot G. 8 × DDR3 ECC DIMM slots
B. GPIO header H. 6 × PCI Express slots
C. mPCIe slot I. AST2400 BMC with HDMI video
D. 8 × 6 Gbps internal SATA J. Integrated I/O
E. 2-port USB 3.0 header K. 1 × socketed POWER8 SCM
F. 2 × internal USB 3.0

OMI Option C - OMI riser cards, DDR4/DDR5 modules

A more flexible but more expensive alternative could be to have riser cards which themselves use standard DDR4/DDR5 memory. This could let you switch out the riser interface when DDR5 becomes available rather than switching out the entire mainboard.

I am taking inspiration from what the Russian company Yadro did for its Vesnin POWER8 machine (@olddellian mentioned these earlier in this thread).

Conclusion

My guess is that Raptor will take the option B approach, and may be waiting until 2022 for DDR5 to reach mainstream (more or less), rather than release a board that will only work with DDR4. On the off chance that OMI really appears to be taking off in 2021, they could change plans and switch to option A and release an OMI-module board instead.

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Raptor-specific speculation aside, Timothy Prickett Morgan at Next Platform tends to be quite knowledgeable about POWER and IBM, so I shall to link his article:

Well I’ve got to say, I’m very impressed by the design of POWER10 overall, but I’m naturally disappointed by the fact that Raptor won’t be able to get a product out to enthusiasts based on the new chip in the near future. I’m really hoping for the best, because I sold my Blackbird in anticipation for either the Condor (which was recently cancelled) or a board using POWER10 instead.

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There is credible (in my opinion) suspicion that Raptor may in fact be concerned about part of the firmware stack being closed-source, or in some other way not owner-controllable.

The tweet reeks of an NDA being in place, and the court of public opinion doesn’t look too kindly on those that enforce NDA’s too harshly.

I’m really curious to see what RCS has to say about what anti-features their current product lineup lacks.

I sold my Blackbird in anticipation for either the Condor (which was recently cancelled)

Source on this, please? I’ve been waiting for this release, which I assumed was in the near future. If RCS has cancelled the Condor and isn’t rolling out Power10 based system to fill that niche, then it’s looking a lot like there are no compelling Power-based systems on the consumer front for the next few years.

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I can’t paste direct links here, but there is a story about the Condor’s cancelation on talospace, Cameron Kaiser’s POWER blog. I’d suggest giving that a read.

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[T]here is a story about the Condor’s cancelation on talospace, Cameron Kaiser’s POWER blog.

Thanks!

It looks like the cancellation post was already linked in the thread, I just missed it.