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The Bleeding Edge [Semiconductor Foundry Thread]



I guess so, but there are too many legal loopholes.


“Good progress” = 3-4 years delayed?

No intel, you don’t have the Steve Jobs Reality Distortion Field ™.

Like 14nm+++(+, +++)?


Let’s not give up hopes on them. They could be able to squeeze out something for a limited range just so their investors don’t fall for an Elon Musk. But I have heard that the 10nm manufacturing process is basically a layer or 2 of 7nm wafers. So I think once they finally got out of the troubling 10nm process, Intel could then focus on 7nm.


This is what I pulled from the conference call, which all media covering Intel did not discuss:

  1. constrained growth in Q4; lower end PC and IoT constrained the most
  2. increased R&D to 13.5B or around there
  3. constrained in 2019 because signals show that they can’t meet demand next year
  4. Intel is looking to find what 14nm demand is to estimate level of constraint
  5. depending on how progress on 7nm goes, they may change capex
  6. logic capex up, memory down - so trying to get chips on 10nm and beyond
  7. reiterated not too constrained PC side, Q4 is where constraints hit more
  8. Cooper Lake still on for middle next year
    headwinds - growing competition, global trade (china and tariffs), wait and see, says manage and weather the dynamics blah

So, they clearly stated that the limits they have and constraints on supply start hitting this Q4, that they are worried about AMDs products into next year may dry up demand for 14nm designs (but that actually alleviates their constraints, as lower demand due to competition means they have better supply to meet that demand and therefore would be less constrained), that they are burning R&D to get 10nm working and are investigating if 7nm is working well enough to pull it in from risk production around 2021 with EUV also being examined for when they can deploy it, that they are focusing their expenditures getting working CPUs, not on memory products like Optane, and that next year may be a really bad year for them.

This came from statements in the Q&A session of the earnings call. Don’t believe me?

I ignore the fluff and go directly to what matters beyond next quarter. This is Intel, as nicely as they can, saying that they are fearful in a couple key regards. If an investment journalist or analyst was worth their weight, they would have brought up those key statements from Intel’s call. How many did you see report on that?

But back on topic, if you match Intel’s statements with the rumor of 10nm being scrapped, they likely plan to call something else 10nm, but it will not be their originally planned process, they are looking at trying to jump ahead with how badly things are going on 10nm, and they are hoping their 14nm++ process will be competitive enough to hold AMD at bay, which will be using TSMC’s 7nm process.

Now, what we know to date from rumors and leaks are that AMD’s uarch, with whatever changes may be present to the IMC, the interconnect, the cache system, the cores themselves, a potential uncore chip, etc., that these changes amount to an additional approximate 13% IPC (original rumor was 10-15%, last leak was 13% in math and science computational workloads in a server setting; remember, IPC varies by task, so this isn’t hard and fast).

Beyond that rumor was the rumor that early silicon is running at 4.0GHz base, 4.5GHz boost, which was purposefully leaked by a person in the Radeon Tech Group in mid September. Looking at Zen 1, 3GHz base and 3.4GHz all core boost was seen at the December Horizon event and at CES, with the final silicon having like a 3.7 or 3.8GHz boost on mainstream consumer silicon. Instead of the outlandish 5GHz claims (5GHz came from GF documents stating they were targeting 5GHz for HPC chips on 7nm, but GF’s 7nm was scrapped and AMD went with TSMC, so all related to 5GHz before that time went out the window). Let’s instead estimate final silicon has and all core boost around 4.5 to 4.6GHz, around 10%.

If you take the 10% speed boost (1.1), multiplied by the IPC boost from uarch tweaks (1.13), you would estimate between architecture changes and process changes that overall performance on AMD’s side will come in around 24%, give or take depending on workload, which, oddly enough, barely places those chips with single digit advantage over Intel’s 14nm++ process with the current skylake iterative architecture.

Above, I posted from Intel’s 2017 press day documents showing that Intel, on their original timeline, predicted that 14nm++ would have a slight performance edge for transistors over 10nm+. Intel even said, at that time over a year and a half ago, that they were targeting 25% performance AND 50% power reduction for 10nm over their 14nm processes. We all know the chart with the power reduction at iso-performance or increased performance at isopower. Instead of giving the chart showing the line, Intel said their specific target on that graph.

Since then, we’ve seen Intel have to make changes to the 10nm process to try to get it working, along with countless setbacks. One account says Intel is focusing on the inclusion of materials like Cobalt and ruthenium for their process while others are focusing on the inclusion of EUV. Truth is, everyone will have to do both of those at some point to move to the 3nm and beyond designs. So nothing wrong with choosing one or the other, and Intel likely took the material sciences approach after being burned since 2015 on not having EUV ready to use.

So, focusing on the derision surrounding the “good progress” language missed out on what was said in the phone call and the likely state of affairs of the 10nm and 7nm processes at Intel and what may happen moving forward related to its process technology.


Kirin 980 die shot (TSMC 7nm)

74,13mm² die
6.9B transistors

93MTr/mm², TSMC 7nm is looking pretty damn good.
Can’t wait for 7nm GPUs and ryzen CPUs on this node.


Seeing the better density is nice. Now, I believe it was mentioned somewhere that due to AMD libraries, the density is only around double rather than higher theoretical limits. Don’t know if true or not, but have seen that in passing. But it is exciting and proof that TSMC 7nm is doing well!


Intel 7nm on track, according to themselves


So, according to schedule means, 7nm in 2019. This is good. We’re going to see some real competition for the first time in a decade!


According to intel a few months ago, for the past 3+ years 10nm has been fine.



Official news on the POWER10 chips using Samsung’s 7 nm:

Wikichip also has an article if you want to read something less corporate:

The POWER and PowerPC General Discussion / News Thread

Its interesting because what little I know about IBM’s mainframes is what I learnt since they bought redhat. A Phoronixs test a few months ago put these mainframe machines running containers on par with AMD, Intel.

So 7nm CPU’s will keep them on track with AMD and well Intel at the end of next year may be back as well.


At long last a look at Intel 10nm and cannon lake.


Just finished reading the article, highly recommended if you’re interested in semiconductors and how Intel measures up to TSMC and Samsung (spoiler; they are very equal).

It also gladdens me to see that anandtech did exactly what I requested a while back


Well. Sort of. In reality, TSMC is building chips the size of Vega and Epyc / 8 core Zepplin dies. And by all reports, getting better than expected yields, and talk of running at up to 5GHz.

Intel can barely shit out a dual core mobile APU, with a broken on-die GPU on it - running at sub 3Ghz.

Irrespective of whether or not the process is good when it works, intel’s process is so badly broken (in terms of manufacturing) that they can’t actually build anything in volume with it.


Yeah, Intels process is much less mature. We’ve known that for ages though.


Don’t know if this is relevant but:

Initially EUV scanners will be used for non-critical layers, but their use will be expanded at the 5 nm node in 2020 – 2021. TSMC says that virtually all customers that use its N7 fabrication process will also use its N5 technology for their next-gen chips.

According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month.


I’d argue that it is likely MORE mature, in terms of time they’ve spent on it. It’s just broken by design (due to the number of steps required as i understand it there’s a huge opportunity for any step to fail and cause the entire process to be a failure), and TSMC isn’t.


I was thinking mature as in functionality.

They’ve got a shit node and should feel shitty.

Move on Intel. You’re missing the boat.


We’ll see once ice lake comes out at the end of this year.

No doubt TSMC is in the lead right now.