I’ve heard several simplified explanations regarding how DDR5 differs from DDR4 (e.g. it has two lower-width channels per DIMM), but I’d like to understand the difference between the two in detail, and the implications of those differences for low-level programming. Does anybody know of a good source for information like this?
Surely there’s more to it than just higher transfer rates… otherwise why call it DDR5-4800 instead of just DDR-4800?
Yes I’ve tried google… I’m sure there’s something technical buried behind the very large pile of simplified explanations, but I haven’t found it yet. Thanks in advance.
Platform memory controller is going to contribute significantly more to low-level memory access performance than DDR4 vs DDR5. It’s fairly appropriate to just treat it as faster DDR4 until platform memory controller has been characterized.
The most notable difference between DDR4 and DDR5 is the state of ECC; I can’t even find a definitive source that outlines what is going on with it, I don’t see 80bit ECC for UDIMMs under the JEDEC JESD401-5A but I’m pretty sure they exist.
That’s a fair point… A better question would be, where might I find good information about how specific memory controllers and cache implementations behave? I guess I’m looking for an Agner Fog style source, but for memory performance…