Imagine if you can have L1/L2/L3$ with multiple Vertical Layers on your CPU in the future.
That can have dramatic impacts on performance.
Especially SMT IMO. Think of SMT4 or SMT8 scenarios in future CPUs.
I’m imagining a future where the main Cores Register can treat each SRAM Layer’s Cache as exclusive for a specific thread.
This can improve “Thread Security” from Spectre/MeltDown like attack vectors because each “Thread” wouldn’t be allowed to peep into another Thread/Layer’s space via hardware security logic and enforce separation.
Dedicated L1/L2/L3 $ portions that are all exclusive and can operate without having to really “Load/Flush” while in the main Core Registers.
The Core’s Main Registers will work on each Thread and won’t have to waste cycles on Flushing and Loading new Data into L1/L2/L3.
A separate piece of helper logic can take care of L1/L2/L3 $ Loading/Flushing while the main registers are busy doing the main compute work.
Ergo minimizing Idle Time between threads.
Is this a viable scenario in the future with this tech?