Any proud owner of 3900x could post lscpu -e output? Would like to know which and how many cores share L3 cache.
lstopo would also be interesting to look at.
Don’t have 3900x, but heres an lstopo for the 3700x
3900x will have 2 packages, with 3 physical in cores active in each sub 4 core grouping
It’s an acronym “Fixed that for you”
But I may be totally off the mark as to Maze’s intention… other than he’s linking to the AMD website for 3900x
I should have clarified:
3900x has 2 CCX’s, each CCX has 2 sets of 4 cores each. 3 of the cores are on each 4 core segments is active, 6 cores per CCX
The chip on the top right, does not look like 4core groups but one 8 core group to me.
2 CCDs each containing two CCXs, I believe is how it breaks down on the newer ones.
Yes, this is what I was getting at based
Thank you for the info.
3950 | -> CCD0 | -> CCX0 -> 4 Cores | -> CCX1 -> 4 Cores | -> CCD1 | -> CCX2 -> 4 Cores | -> CCX3 -> 4 Cores 3900 | -> CCD0 | -> CCX0 -> 3 Cores | -> CCX1 -> 3 Cores | -> CCD1 | -> CCX2 -> 3 Cores | -> CCX3 -> 3 Cores 3700/3800 | -> CCD0 | -> CCX0 -> 4 Cores | -> CCX1 -> 4 Cores 3600 | -> CCD0 | -> CCX0 -> 3 Cores | -> CCX1 -> 3 Cores
Inb4 3core phenoms again
I suspect what you are looking as “cores” are actually something else. Like maybe 2xL2 cache regions for each of the larger “cores” on the outside of the die.
Zen2 has massive caches, it would not surprise me if most of the die is actually cache.
One package, 3 dies.
IO die + 2 CCDs
Each CCD has to CCXs for a total of 4 CCXs.
Each CCX has 3 active cores for a total of 12 cores.
No, 6 per CCD, 3 per CCX
CCD is the Die.
CCX is the 4 Core Block, of wich 2 are “glued together” in the die.
Also regarding CCX interconnect inside a CCD: The 2 CCX’s are connected via a very fast cache crossbar so for all intents and purposes 2 side by side CCX’s within a CCD behave like one big CCX. The reason its got 2x 4core CCX instead of a single 8 core CCX just has to do with simplifying cache area and cache-core design. An 8 core CCX can be done but has effects on power consumption, defect rates and cache associativity.
Yeah, increased complexety, that doesn’t scale well.
Wasn’t it the power of 2 in complexety?? So 4 times the Crossbar?
When everything is connected to everything, that really increases the Transistorcount and also power consumption.
It would have been nice but I understand why they will stick with 4 Cores per CCX - because its the biggest they can go without scrapping the efficiency. 8 Cores have 4 times the complexety and also need more interconnects and so on…
Some new stuff today