I have built a new PC around the Ryzen 7 9700X with 2x 32GB DDR5-6000 C30, RTX 4080 Super and a 4TB SN850X. The first thing I did after building was checking for stability of course. My first test was y-cruncher 0.8.5 Build 9543. I enabled all tests and started stressing. Through pure coincidence I noticed that the CPU is running at 3.55GHz during some tests. I think this is strange since the base clock is 3.8GHz!
I have a power meter on the wall and it consistently draws 155W - 160W. This is why I believe this is not a temperature issue but maybe a power limit issue with AVX512? I also included an overview picture of the build so that you get an idea what cooling is available to the system.
Thank you very much for your reply. Enabling PBO can be done for testing. But I actually wanted an 88W PPT CPU so it runs cool and quiet. I posted this because I think this is not intended stock behavior.
Skatterbencher was only able to run their 9700x at 4.1GHz under OCCT AVX2 load on stock settings.
Not sure how much of y-cruncher is avx512, but it seems plausible that if a large portion of it was, that the clocks could be even lower than an avx2 workload.
While CB2024 does have some of the more advanced AVX instructions, it doesnāt seem to use them as often as y-cruncher ā I remember reading this in a chipsandcheese article.
That could explain the clock discrepancy in CB2024 vs the OCCT AVX2 test that skatterbencher showed.
I have started HWiNFO along with y-cruncherand it is at 100% PPT limit all the time. The die temperature never exceeds 70Ā°C even though itās 27Ā°C ambient. It works, it is stable but I think the clocks are lower than intended.
That definitely sounds like its bumping up against the stock power limit and not a thermal limit.
There is some variability it clocks that CPUs can achieve under workload from sample to sample, but historically itās only a couple hundred MHz max, silicon lottery and all.
So, lots of AVX512. But the real reason for the downclock is most likely that the memory channels are so much undersized that the CPU is mostly waiting for data to arrive (up to 400 cycles per AVX512 command).
DDR limitationās what I was anticipating. On Zen 4 I easily got +40% updating compute kernels from AVX to AVX-512 but for most workloads that scaled only to a couple active cores. Often at 4+ cores AVX10.1/256 would net higher throughput. Iād put Alexanderās comment at the end about 4-8 channels a little differently in that architectures capable of utilizing 1+ channel/core mean whichever of AMD and Intel moves to a quad channel desktop socket first will pick up a significant generational win.
Over the past week and some itās been increasingly feeling to me like Zen 5ās design priorities were EPYC, Threadripper, and Ryzen in declining order.
Iād suggest checking also EDC and maybe TDC. In my experience Zen 3 and 4 multicore AVX(-512)'s often EDC, rather than PPT, limited.
Thank you very much. I have observed through HWiNFO and a wattmeter on the wall that its hitting a PPT limit though. When I enabled PBO it was running at 4.4GHz instead of 3.55GHz in y-cruncher.
