This is where the guys at AMD seem to disagree and I think they are right. Multi-chip GPUs in gaming need to be able to stand on their own feet. Developers are unlikely to put in the work to support that kind of solution (which I can understand considering the work involved and the possibility that the overall design may change in a 4 year timeframe). There is no indication that is going to change in the future.
Now, I would not dismiss the possibility of a multi die GPU with a central IO die and cache being able to work well in gaming workloads. The question is, can AMD make it cost efficent. This seems to be overall harder than on the CPU side.
Give it 5 years and youâll have an APU that does 4k60 stable with local HBM cache for your entire system memory (if required) as GPU memory. Maybe slightly more than 5. But definitely well less than 10.
edit:
The saving grace for multi-GPU may actually be ray-tracing.
Ray tracing is one of those âembarassingly parallelâ problems. If you could throw one (or even more) processor per pixel at the problem, you could make it go faster⌠i mean just look at what the big boys like Pixar doâŚ
edit2: @SgtAwesomesauce
Actually the PS5 is supposed to be a 4k60 machine. That will be out in 2-3 years, tops. That wonât be a threadripper based machine, that will be a cut down ryzen 2 APU. So yeah. Not far off. At all. And it wonât be $1200. Nearer 1/3-1/2 that.
I think we are going to see direct die liquid cooling solutions (from the factory) in the future. Itâs an obvious step, to get every last bit of performance and efficency.
I actually confirmed this inadvertently when my GTX760 died (relatively) recently in my i5 system and the last decent card i had still laying around was an 8800GTS.
It was barely as fast in some instances and vastly outperformed in others by⌠drum rollâŚ
HD4200 iGPU on my haswell i5.
Pretty sure i bought the 8800GTS less than 10 years ago. It was a very close to top of the line card. HD4200 wasnât even fast by iGPU standards when it was new.
edit: looks like iâm off. i likely bought the 8800GTS prior to 2008. But close⌠Mine was a 320 MB card.
This does not add up.
The I/O die (confirmed by AMD to be that) does not have any CCX in there.
This is what most here (and the video) have been saying. 8 cores get fed from 1/4 the I/O die. Meaning every I/O die with one woring quadrant can be salvaged.
For TR, there may be half the die. Allthough looking how Rome has 2 Core Chiplets per quadrant of I/O die, that may not be needed unless AMD goes beyond 16 cores.
I think that is still the most up to date and in-depth look at the I/O die and Rome setup we have so far. Even if scalability of the I/O die was reduced from 8 pieces down to 4.
The full IO die feeds 8 chiplets (each 8 cores) in Epyc.
ONE Zen2 chiplet is 8 cores.
1/4 of the IO die can feed two chiplets. Ergo, Ryzen is going to be 1/4 IO die and 2 chiplets for UP TO (linus x299 rain video) 16 cores on AM4.
8 core Ryzen 2 (i.e., something competitive with the Intel i9-9700k) will be 2x up to 50% broken Chiplets, with an IO die that could have been up to 75% damaged (but more likely less damaged than that and other quadrants sliced off for other Ryzens or possibly a Threadripper got half an IO die). Assuming of course that â50%â and â75%â damaged mean in terms of working sectors of the die, as opposed to 50-75% random distribution of defects on the die.
Making something competitive with high end consumer intel parts out of 50-75% broken shit = genius
I suspect that AMDs effective (i.e., the silicon they can use for âsomethingâ instead of throwing it out) yields are going to be so great doing this that the <8 core Ryzen 3000 series parts would have been deliberately crippled in order to get the core count that low.
Their potential yields doing this are going to be THAT good.
PS5 will likely be 1 ryzen chiplet, 1/4 IO die and a Navi chipletâŚ
My favourite part if that is the Thread Ripper possibilities.
I am sure some are thinking right now that this has to be nonsense as 16cores on AM4 would eat TR4 alive⌠But if they can do 16 on am4, what could they load into a TR4 socket? I know they are showing 64c/96t (even writing that made me woah) EPYC, so the is potential for that on TR4 but easily a 32c/64t thread ripper, again woah. Workstations are a whole other world from even 2 years ago now.
adored in his video clearly states half of the IO chip - and i dispute that; Not to mention its unknown if you can even split that chip - according to what we saw you cannot.
comparing sizes proves something else.
The pci-e lanes etc on ryzen 1 die has been disabled (not produced smaller) - chiplets arenât smaller than epyc or tr dies at all. You wouldnât have them smaller. They will be exact same size.
Why half the die? Regardless of what he said we and him both know that each âquarterâ can support 2 8core chiplets. So why the need for half with the capability to run 4 chiplets and 32 cores on AM4 socket. In TR4 sure but not AM4, they only need a quarter of the io die functioning.
I said functioning for a reason, because the next thing is splitting the chip. I donât thing any means physically splitting it but that it has 4 functional quarters. So for the AM4 CPUs 3/4 of the IO die could be defective and dead. They only need one quarter to run the show. They can fuse off the other 3 and âsplitâ the chip that way. So it will take up space sure but it only needs to be literally minimally functional to be usable. There is room enough for the chiplets next to it by the looks of it, but I am not laser eye ball augmented.
Edits:
Do you mean the new Rome Epyc or the older Zeppelin based ones. Because the new 8 core chiplets are half the size of the old Zeppelin chips.
If you mean the new Rome ones than yeah of course they will be the same size, no body is debating that.
âChiplet Architectureâ is the design approach, contrary to the traditionall âmonolithicâ system.
The CCXs on Rome/Zen2 are a quarter the size (halfed width and depth) allowing 8 cores where Zen1 (Ryzen 1000 and 2000) only had 4.
The PCIe, DDR4 and I/O controlls have been moved to a dedicated I/O die shrinking the chips with CCXs even further.
You mean like there never will be 8c/16t cpus for $220?
Zen2 will be made on TSMC 7nm wich they claim delivers 20% more speed.
The 2700X boosts to what? 4.3GHz? That would then be 4.3 x 1.2 = 5.16GHz boost. Not too bad.
Depending on what AMD did to the architecture, I would say 5.2GHz on 4 cores is feasible.
Price point: Cheaper than Intel (by 30-ish percent).
Dream territory on AM4, but if they can fit the 220W power target (not to be confused with 180W TDP), then maybe on TR4?
That is also hugely inflated because Intel have been able to do that for the longest time, because we let them and had no choice. I wonder what the real price for them could be if they were not gouging the market.
I imagine their margins are enormous, but if AMD were to cut those margins to the quick, everybody would bleed including AMD. They need to release a great product and undercut Intel enough to sell, but still make as much money as possible off each sale.
