Hello Logan and Wendell

I have some thoughts on the trend of critical infrastructure, and other such vital systems that if they fail people will die, going to RISC processors (such as ARM, PPC, Etc.) My thoughts are that since RISC processing is a simple and reduced instruction set that requires more lines of code to do the same algorithm as CISC, would this not cause as problem? As you both know RISC is more software dependent and CISC is more hardware dependent. Being that Software bugs/errors are far more common than Hardware bugs/errors, wouldn't having medical machines, infrastructure, airplane control towers, car airbag sensors, car black boxes, and other devices to help save lives, being switched to RISC processors be far more prone to error. I recently heard that the control systems in the Nuclear power plant in my city plans to switch to ARM, and other RISC platform chips. I do not feel comfortable having the software that can prevent a full nuclear meltdown relying on algorithms that have to be reduced to their basic functions, then compiled then have the next set reduced, etc. then compiled to the mathematical solution that a CISC processor such as Intel, and AMD x86/64 can do with not only less steps, but can also handle the algorithm without the algorithm being reduced to simpler, reduced instructions.

What are your thoughts on this, am I worrying too much over nothing, or do I have a valid reason to worry about this trend of critical systems going from CISC to RISC?

Thank You


Zoltan would love this post.

Here is my take on the issue. Computer code is only as good as the person writing it. This is true of all software code. RISC vs CISC won't change this, there will always still be a human being writing the software code and humans are prone to the occasional error.

So, when compiling for CISC, the instructions get reduced to RISC instructions in hardware while compiling for RISC will directly produce RISC instructions and the hardware can execute them directly. For code compiled for RISC architectures the compiler has to role of the micro-op.

I don't see why this should be more error prone than a hardware implementation.

Also, if you write the code in a high level language, it is the same. If the compiler doesn't fuck something up there shouldn't be a problem at all on both CISC and RISC.

Maybe I'm missing something. Someone has got more insight in this?

First of all, there isn't all that clear of a separation between CISC and RISC anymore, I believe I posted already about that stuff.

Second of all, since the early 2000's the instructions of processors are encrypted, whereas before they weren't. This has to do with legal stuff, but it's a crime, because it means that the true effects of a processor cannot be examined anymore. Coincidently the encryption of processor instructions was started just after the infamous "third key" was discovered, that Microsoft itself didn't know was hidden into the Windows code (I laughed for days when that news came out, I was using GNU/Linux for three years already then as main OS), as it was probably a heritage of IBM (Windows NT is the IBM OS/2 project taken over by Microsoft). So in short, the real reliability performance of processors can't be objectively checked anymore, except on CPUs that use unencrypted open source instructions, which are mostly a limited number of RISC processors.

Thirdly, there are pretty good reliability statistics comparing Intel Xeon and IBM PowerPC platforms in big data applications, and the PowerPC is more than 5 times more reliable in a GNU/Linux environment.

Interesting. What means reliable in the context? Do you have the source of the stats?

Yes I do have a source, the fact that RISC is more software dependent is actually listed at 


Sorry didn't see that post, yes it was a report by Solitaire Interglobal Ltd on the Power7 and PowerLinux platforms running linux, against competitive solutions on other platforms, I have to search for it, but I will post the report when I do. It was an allround very longterm test with several thousands of benchmarks combined, quite impressive actually.

I thought that RISC is Reduced Instruction Set (forgot the last part). Its not a reduced instruction set but a reduced instruction set. Meaning there's not fewer instructions. I saw that somewhere when I was researching this topic. I hope that made sense

Thank you guys, and I appreciate all the answers, and look forward to more thank you 

Do you mind linking the source to that encryption claim?  I am having trouble finding it... I think I'm over looking it.

Sure, np (yeah it's very old, and most English language links were removed from the internet):


The Cryptonym report was removed from the internet many years ago (lolz), but there are still copies out there... just "!g" ddg.gg them...

Well, that not only made for an interesting read, but it also is a good indicator I need to brush up on my German.