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Question regarding something wendell said in "Headless PCIe Passthrough"


#1

@wendell

In this YT video https://www.youtube.com/watch?v=1MI1s4hZ_yE you mentioned that there are differences in the PCIe allocation or something between TR 1900X and 1920X,1950X? As the video is now cut I can’t access the part where you mentioned it. What are those differences? As I use a 1900X currently I’m very interested in that and was a bit baffled when you said it but I couldn’t find anything about that in my search.


#2

Just that on some board the IOMMU groups combine one nvme with one pcie slot and that sometimes you have to juggle that


#3

But isn’t that board specific and not CPU specific?


#4

Yep, but in the 1900x it remains to be seen because half the pcie resources come from the deactivated die


#5

Oh, so it’s not a 4+4 but a 8+0 Die layout?


#6

Nope it is 4x4 I believe what @wendell ment was that 1900x has the same amount of pcie lanes as 1950x which is 8x8 and should have 64 pcie lanes. So in the case of 1900x it should mean that half the pcie lanes are coming from the disabled cores.

This is just my speculations based on that epyc 32 core processors have 128 pcie lanes and what Wendell said in this conversation.


#7

Oh ok, so CCX+0xCCX+0 and since we still have the PCIe lanes of the 0`s it may get weird when accesing stuff over those.


#8

Yeah at least I think he is talking about this. I don’t own a threadripper to test it.