Qemu Ryzen 7000 CPU cache size in VM wrong?

Hi,

I plan to buy Ryzen 7000 system, now I noticed that in the systems I have seen so far, the VM CPU cache sizes are not correct.
I saw a 5700G system where Windows showed 128MB 3Level cache and this Zen4 7700 System shows only 16MB 3Level cache and 512KB 2 Level cache.

coreinfo

Logical Processor to Cache Map:
**----------  Data Cache          0, Level 1,   64 KB, Assoc   2, LineSize  64
**----------  Instruction Cache   0, Level 1,   64 KB, Assoc   2, LineSize  64
**----------  Unified Cache       0, Level 2,  512 KB, Assoc  16, LineSize  64
************  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
--**--------  Data Cache          1, Level 1,   64 KB, Assoc   2, LineSize  64
--**--------  Instruction Cache   1, Level 1,   64 KB, Assoc   2, LineSize  64
--**--------  Unified Cache       2, Level 2,  512 KB, Assoc  16, LineSize  64
----**------  Data Cache          2, Level 1,   64 KB, Assoc   2, LineSize  64
----**------  Instruction Cache   2, Level 1,   64 KB, Assoc   2, LineSize  64
----**------  Unified Cache       3, Level 2,  512 KB, Assoc  16, LineSize  64
------**----  Data Cache          3, Level 1,   64 KB, Assoc   2, LineSize  64
------**----  Instruction Cache   3, Level 1,   64 KB, Assoc   2, LineSize  64
------**----  Unified Cache       4, Level 2,  512 KB, Assoc  16, LineSize  64
--------**--  Data Cache          4, Level 1,   64 KB, Assoc   2, LineSize  64
--------**--  Instruction Cache   4, Level 1,   64 KB, Assoc   2, LineSize  64
--------**--  Unified Cache       5, Level 2,  512 KB, Assoc  16, LineSize  64
----------**  Data Cache          5, Level 1,   64 KB, Assoc   2, LineSize  64
----------**  Instruction Cache   5, Level 1,   64 KB, Assoc   2, LineSize  64
----------**  Unified Cache       6, Level 2,  512 KB, Assoc  16, LineSize  64

Logical Processor to Group Map:
************ Group 0

A Ryzen 7700 has 32MB 3Level cache and 1MB (8MB) 2Level cache.
If this is not a one-off case, why is no one talking about it?

I got an AM4 test system and with the right libvirt config the cache sizes are right. The wrong cache values I had seen were with Proxmox.

QEMU need to be patched to support ever changing AMD’s CPU topology…

Check the archive of QEMU dev mailing list. See if Ryzen 7000 supported properly already or someone enterprising already posted a patch.

For my Windows 11 VM it’s correct. I’m passing 1 CCD of my 7950x and this is the result:

Logical Processor to Cache Map:
**--------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Unified Cache       0, Level 2,    1 MB, Assoc   8, LineSize  64
****************  Unified Cache       1, Level 3,   32 MB, Assoc  16, LineSize  64
--**------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Unified Cache       2, Level 2,    1 MB, Assoc   8, LineSize  64
----**----------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Unified Cache       3, Level 2,    1 MB, Assoc   8, LineSize  64
------**--------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Unified Cache       4, Level 2,    1 MB, Assoc   8, LineSize  64
--------**------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------  Instruction Cache   4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------  Unified Cache       5, Level 2,    1 MB, Assoc   8, LineSize  64
----------**----  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----  Instruction Cache   5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----  Unified Cache       6, Level 2,    1 MB, Assoc   8, LineSize  64
------------**--  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--  Instruction Cache   6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--  Unified Cache       7, Level 2,    1 MB, Assoc   8, LineSize  64
--------------**  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**  Instruction Cache   7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**  Unified Cache       8, Level 2,    1 MB, Assoc   8, LineSize  64

When I pass more cores it is still correct.

qemu version:

QEMU emulator version 7.0.0 (qemu-7.0.0-13.fc37)
Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers

I’m using cache mode passthrough:

  <cpu mode="host-passthrough" check="none" migratable="on">
    <topology sockets="1" dies="1" cores="8" threads="2"/>
    <cache mode="passthrough"/>
    <feature policy="require" name="topoext"/>
  </cpu>