A 5700 XT is plenty for 1080p60fps, and should be fine for new games for at least a couple of years. Well, it should be fine, unless the new consoles make new games much harder to run, but who knows.
x570 based boards generally have better IOMMU groups. B550 AFAIK can generally separate out the two physical x16 slots into their own groups, but everything else is in one or two groups which is not ideal.
Not the same board, but it should be similar because of also being B550
Don’t forget that AMD cards have the reset bug. There is a patch, but only partially works, and still has issues.
Navi Reset
What this does is use powerplay tables to turn the card off and back on again. (Insert IT crowd meme here, haha).
@gnif has done it again. Good work!!
Ok, here is the navi reset. Navi is easier to implement as the SMU has most of the logic in it.
Update 27-11-2019: Updated patch down below: Navi Reset Kernel Patch
From 69ea42207b544b6e3fa9755022bff09d2ce953d9 Mon Sep 17 00:00:00 2001
From: Geoffrey McRae <[email protected] >
Date: Thu, 12 Sep 2019 03:19:28 +1000
Subject: [PATCH] pci quirk: AMD Navi 10 series vendor specific reset
Signed-off-by: Geoffrey McRae <[email protected] >
---
drivers/pci/quirks.c | 98 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 44c4ae1abd00..d94ddb1c6832 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3825,6 +3825,97 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
return 0;
}
+/*
+ * AMD Navi 10 series GPUs require a vendor specific reset procedure.
+ * According to AMD a PSP mode 2 reset should be enough however at this
+ * time the details of how to perform this are not available to us.
+ * Instead we can signal the SMU to enter and exit BACO which has the same
+ * desired effect.
+ */
+static int reset_amd_navi10(struct pci_dev *dev, int probe)
+{
+ const int mmMP0_SMN_C2PMSG_81 = 0x16091;
+ const int mmMP1_SMN_C2PMSG_66 = 0x16282;
+ const int mmMP1_SMN_C2PMSG_82 = 0x16292;
+ const int mmMP1_SMN_C2PMSG_90 = 0x1629a;
+
+ u16 cfg;
+ resource_size_t mmio_base, mmio_size;
+ uint32_t __iomem * mmio;
+ unsigned int sol;
+ unsigned int timeout;
+
+ /* bus resets still cause navi to flake out */
+ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
+
+ if (probe)
+ return 0;
+
+ /* save the PCI state and enable memory access */
+ pci_save_state(dev);
+ pci_read_config_word(dev, PCI_COMMAND, &cfg);
+ pci_write_config_word(dev, PCI_COMMAND, cfg | PCI_COMMAND_MEMORY);
+
+ /* map BAR5 …
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