Your first projects aren’t the greatest things in the world, and they may have no money value, they may go nowhere, but that is how you learn – you put so much effort into making something right if it is for yourself.
— Steve Wozniak
Goals & Features :
- Bare minimum Instruction sets “G + A + C” (General Compute, Atomic, Compress)
- RISC-V cores from scratch. SW Emulation >> HW
- Dynamically combine or remove cores from an user’s instance. (post bitstream)
- Isolated cores.
- Access cores via HW gui or over IP
- Half decent documentation. (It’s important.)
- Performance and efficiency metrics
- Website with webcam display for FPGA and an embedded VM
- Emulator testing with Gitlab CI
- Learn and help others learn.
- Finish it.
How do you design a RISC-V Processor? Where do you start?
The entirety of the PaRsk Project, including the learning process; will be documented(or I will at least try to). Which makes learning about RISC-V design a more streamlined, concise, and fun. I assume the reader has a basic understanding of FPGAs, computer architecture & design, and HDLs. If not, feel free to review the links below.
RISC-V is open source; the future of efficient processing. And what is open source should be open to the public to easily learn. So tag along and join my on this RISC journey!
The RISC-V Instruction Specs
RISC-V Main Github Page
RISC-V Reference Card (Instruction set cheat sheet)
Wiki: RISC Extension Naming Scheme
Paper: Optimized RISC-V Five-Sage Pipelining
YouTube Playlist: LMARV-1 Hardware RISC-V! (contains bugs, but is fixed)
YouTube Playlist: LMARV-1: reboot/redesign
PDF: RISC-V CPU Control, Pipelining Single-Cycle RV32-I
YouTube Playlist: Ben Eater’s 8-Bit Breadboard CPU!
YouTube Playlist: MIPS Single-Cycle Architecture
YouTube Playlist: [CSCE 611 Fall 2020]
Digital Design and Computer Architecture (Good intro, but uses MIPS for CPU portion)
Great Book on SystemVerilog: Simulation & Synthesis
Computer Architecture: A Quantitative Approach – 6th Edition