RISC-V (pronounced “risk-five”) is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
In contrast to most ISAs, the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes a usual weakness of new instruction sets.
The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers and industry workers outside the university.[1]
The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind,[2][3] but without over-architecting for a particular microarchitecture style.[3][4][5][6]
As of May 2017, version 2.2 of the userspace ISA is fixed and the privileged ISA is available as draft version 1.10.
@lordofthelocusts - What are your thoughts on RISC-V? Providing some of your opinions and elaborating on the topic will likely encourage discussion.
Like I already said it’s the future. Computer hardware is only getting more and more locked down (cell phones being the worst offenders) and we’re in dire need of proper free hardware as well as free software. I believe that proprietary software is morally wrong and that we must make the push to things like RISC-V in order to maintain our freedom.
I am glad that people have interest in this. If we have a common platform, we can see real innovation based on merit of the platform and not based on “Secret Sauce X” which will allow me to sue you into oblivion while also ensuring that I can stagnate the industry.