3.0B transistors @ TSMC, 40nm 2 x 16-way FMA SM, IEEE754-2008, 16 SMs Each SM has four SFUs 384-bit GDDR5 (768Mb-6GB RAM) [color=#ffa500]~650/1700/4200MHz /color 16 pixels clock address and filter per SM 48 ROPs, 8Z/C clock 64KiB L1/smem per SM (48/16 or 16/48 per clock config, not user programmable as far as I know, at least not yet) Unified 768 KiB L2 (not partitioned now, so a write to L2 from any SM is visible to all others immediately) Unified memory space (hardware TLB, 1TiB address, 40-bit if my brain's working)
yeah there will be, but obviously nvidia is aiming more to please the HPC market than the gamer market. however im sure they can juggle both with their wisdom
I think that article is a little fishy. First I wonder who took those pictures? And second I just highly doubt Nvidia is that dumb unless they had a 1.0gpa in engineering. The second and fourth pictures look completely fake also.
yeah i already linked the real pictures. the pictures that were taken at the gpu technology conference, pictures of the card in Huang's hand. its legit, the 8 pin connector is on the end of the card, not the top.