(Had to tag him for this lol)
In all seriousness this looks like on the surface that it might make a dent in Intel's datacenter share with according to some articles they have been obsessing over because that's their cash cow (intel not AMD just to clarify)
:3 cannot wait for this to be a thing. Hopefully it has gobs and gobs of cache.
Gentoo would be so happy if I got her that Naples CPU.
tbh this gets me more hyped up than ryzen. 128 PCIe lanes is quite the difference with the 24 ryzen has to offer. Really curious to see what motherboards for this CPU will be released and at what cost. Would love to see an affordable motherboard without chipset and just a load of RAM and PCIe slots.
if there's a dual-socket option...
drooooooooooooooooool
All of the peripherals, all of the time...
dual socket will definitely be a thing. This article contains slides from a naples demo (article itself is in Dutch though) which shows how dual socket will work. 128 pcie lanes will be used for communication between both the CPU's, the other 128 pcie lanes will be available for I/O. Although 256 pcie lanes for I/O would be ballin'', I like that the amd infinity fabric interconnect allows for direct communication with the CPU's. Lets be honest, 128 lanes for add-in cards should be plenty for now
With PCIe Gen4 around the corner... huehuehuehuehuehue...
but even at AMD prices it'll be absurdly expensive and not worth the cost for what people like me would use it for... ;.;
I hope they make an EATX motherboard with 8 full x16 slots that can all be broken out to dual 8x and quad 4x... that would be amazing.
Would they let mobo makers do a workstation version? All those lanes, all that RAM... Or will there be an 8 core Naples CPU? OH MYYYY!!! ;)
Why should they do that? You want 8 cores capable of handling ECC memory?
Well, RYZEN does that. It just needs a WS board.
Absolutely they have. To get 2x2650v4 cpus, it costs my company a little over US $2000. This is bullshit. It's not even a great CPU.
The way the memory channels are designed, it would be a waste to not have at least 128M of L3.
Based on the way they explained it, it may be 64 lanes per socket. 128 lanes per cpu, but when you put it in a dual socket system, 64 of those lanes on each CPU get used for the "infinity fabric" which is equivalent to intel's QPI. But at this point we're just dogs barking at cars. Not much use to speculate this early.
Not going to be in first gen Naples. Although it's nice to think about, the timing just isn't right.
If I'm understanding the concept behind Naples, it's going to be low speed, high concurrency. Expect 1.8GHz-2.8GHz core speeds for first gen. You won't want to have that in a desktop with only 8 cores. If you are on Linux and have a 16 core system, that would be okay, but the only real reason to go Naples is for dual-socket and boatloads of ram/PCIe lanes.
Did I imagine it? It seems to me that I read somewhere that this CPU will have a RISC architecture. If so, it seems to me that this would suggest BSD and Linux only, for the immediate future ... which wouldn't suck at all, for a workststion machine! Just imagine all of the VM love that you could host on this monster!!!
EDIT:
It seems that I was thinking about the K12 RISC CPU, which was initially, at least, being developed in parallel with Ryzen. I haven't heard any progress updates/ETA's on this project in forever.
128 threads and 2TB (32x64GB) of octa-channel ECC per U.
Do want.
Based on the way they explained it, it may be 64 lanes per socket. 128 lanes per cpu, but when you put it in a dual socket system, 64 of those lanes on each CPU get used for the "infinity fabric" which is equivalent to intel's QPI. But at this point we're just dogs barking at cars. Not much use to speculate this early.
no speculation, added image is a slide from the AMD presentation. What I like about this approach (as opposed to intel QPI) is the direct link between PCIe added cards and the CPU. Very handy for accelerator cards for example.
Oh cool. Thanks for the information.
Good point. I've still only got a 30000ft view of the architecture, so I can't speak to specifics, but it does seem much better for single pci cards that will take advantage of both CPU.
Also, I wonder what effect the PCIe ACS override patch on Linux will have on the infinity fabric. I can't imagine they'd play well that way.
I know it's blasphemy at this forum, but I am a novice when it comes to linux and not familiar with ACS patch. (read the how-to topic on this forum regarding gpu passthrough though)
In the long-haul I would guess this approach by AMD would also be beneficial for linux users though. Because napels is a soc, I would recon differences between motherboards would minimize and one general driver could emerge for all naples motherboards which at least manages the CPU(s) and the PCIe lanes. But please correct me if i'm wrong.
Personally I love the idea of a motherboard with just the sockets and a sh*tload of RAM and PCIe slots. No chipset, no I/O i am not using anyway, no weird proprietary connections/busses, etc. It gives full control over how all PCIe lanes are utilized.
This would be a virtualization beast, already looking forward to 16 gamers 1 CPU from the neighbors at LTT :)
Looks impressive but what fps does it get in Minesweeper on ultra low at 360p. This is important and I need to decide between this and a 7700K. Plz help
Trolling aside this looks like an extremely interesting chip. Especially based on how efficient Ryzen is at lower clock speeds. This could seriously disrupt the data center. The interconnects and Infinity Fabric are interesting as is the memory structure. Wonder how it will play with Vega.
Eh, don't worry about it. I'm more focusing on PCI signalling level interactions anyways. I could spend hours writing about how the patch plays with the way PCIe signalling is optimized.
Yep, Yep, Yep. It's going to be awesome.
As I said above, I think these CPU are going to be low core speed (1.8-2.8GHz) while still having high concurrency. Basically, not that good for gaming.
Depends. Did Microsoft finally optimize Minesweeper to take advantage of more than 32 cores? Come on microshaft, get with the program! Everyone knows it's all about concurrency these days...
My boss and I just had a discussion about what to do when the 2650v2's we have go out of support at the end of the year. If supermicro picks these up, we may go with them for our openstack cluster.
You are probably right, but bear with me here for some very speculative napkin math:
So in order for the naples to be 2x faster than the e5-2699A V4 (clocked at 2.4 ghz) something must be going on:
- AMD is playing dirty and has "sabotaged" the benchmark (crappy cooling on the Intel cpu, undervolted, etc. etc.)
- AMD is playing a bit dirty and has "optimized" the benchmark to favor their naples cpu. (why else some weird secret "seismic analysis" benchmark)
- AMD has put more memory in their system (also undisclosed with the benchmark) which results in the 2x performance gain.
- AMD has put a ridiculously high clocked naples against the 2.4 ghz xeon.
My best guess would be on more memory for the naples system and a bit of optimization. In the last comparison where both systems were configured to the max, the Intel system could not finish the benchmark because of insufficient memory.
So the chance is very slim, but high-clocked naples cpu's could still be a possibility. At least the current info doesn't disprove the existence of high-clocked naples cpu's, or am I missing something here?
I know this all is VERY speculative, but I am bored and I want that hype train going :)
No, the PCIe lanes. 128 of them.
After watching that video, I can only agree with one guy from the comments:
