Hi there,
I am currently writing a Makefile and have run into Problems regarding the use of automatic variables when used in conjunction with ‘eval’. My project structure looks like this:
foo
|-> inc
| |-> header.h
|-> src
| |-> main.c
bar
|-> inc
| |-> header.h
|-> src
| |-> main.c
where foo, bar, inc and src are directories (hopefully its understandable). Now I want my Makefile to build ‘build/foo/main.o’ and ‘build/bar/main.o’. Here is what I’ve tried so far
now when i run make the automatic variables $@ and $^ don’t get properly expanded (in the way they would’ve worked had I not put them inside the TARGET_template). Any Ideas why that is the case and also how do I go about fixing this?
Oh thanks yeah edited the example. I actually got more than just foo and bar as directories and wanted a generic target and their rules that make figures out by evaluating inside the loop and calls the template. I basically wanted to avoid writing this
This is how I build all C files inside all directories inside src. What I do, is I collect all the objs into one list and then just make the binary depend on them.
They actually do build separate binaries. And thus I wanted the object files to live inside their respective subdir inside the build dir. And the problem I am facing is basically only cosmetic, in order to avoid copying some lines of code. The OBJS variable already holds all the required .o files that need to be created.
No problem, thanks for the effort anyway. For now I am just gonna copy the code for everything I need, not to hard after all and I also DO need to get stuff done . I was just hoping someone could help me understand this because it looks like another step forward towards my
‘almighty compile everything effortlessly with this one makefile’ Makefile.