Least noisy reliable HDD

[lemma]

@mattlach

According to AMD’s specs webpage the Threadripper 3960x does not support ECC.

I haven’t worked with a Zen 2 Threadripper but there’s a bunch of back and forth statements saying ECC is not supported, that it is supported, that it’s up to the motherboard, and that support means ECC DIMMs can be used but SECDED won’t be performed (i.e. it’s a marketing claim rather than an engineering one). Unless you’re seeing SECDEDs getting logged I’d tend to assume the latter.

FWIW, I checked back for a strong statement the Zen 2 IMC supports ECC and failed to find one. EDAC seeing 4x16 instead of 4x32 might also be hint for lack of SECDED.

@mattlach

I just realized I typed this reply in a thread with a completely different topic.

Internet subject drift is an art form. And the hard drive discussion seems pretty well over.

[jxdking]

The quietest drives are the drives not spinning. I am talking about spin down the drives when you are not using it.

[mattlach]

@lemma

EDAC seeing 4x16 instead of 4x32 might also be hint for lack of SECDED.

You seem to have a much better understanding of this topic than I do.

What would the consequences of a non-functional SECDED be? Does it completely negate the functioning of the error correction/detection of the ECC RAM?

@lemma

Internet subject drift is an art form.

It’s the art form I am best at

[lemma]

@mattlach

Does it completely negate the functioning of the error correction/detection of the ECC RAM?

For DDR4, yes, barring really exotic parts that ODEC. All an EC4 DIMM does compared to a non-ECC version of the same DIMM is store an extra eight bits per 64 bit word. If the IMC doesn’t stuff those eight bits on writes, read them back, and check them then there’s no end to end ECC over the bus.

Hence the concern over marketing (ECC is totally broken and you might as well just buy regular UDIMMs) and engineering (ECC SECDEDs) definitions of support. Gigabyte’s definitely put the marketing definition in their fine print in the past. So many people have assumed Asus was using the marketing definition it’s got support pages for some DDR5 boards that kind of rant about really actually having end to end checking. I don’t know of a DDR4 equivalent but there might be something in their FAQs.

If you’re feeling particularly suspicious, though, Asus only ever seems to say DDR5 checking and avoids specifically claiming correction support.

[mattlach]

@lemma

For DDR4, yes, barring really exotic parts that ODEC. All an EC4 DIMM does compared to a non-ECC version of the same DIMM is store an extra eight bits per 64 bit word. If the IMC doesn’t stuff those eight bits on writes, read them back, and check them then there’s no end to end ECC over the bus.

Hence the concern over marketing (ECC is totally broken and you might as well just buy regular UDIMMs) and engineering (ECC SECDEDs) definitions of support. Gigabyte’s definitely put the marketing definition in their fine print in the past. So many people have assumed Asus was using the marketing definition it’s got support pages for some DDR5 boards that kind of rant about really actually having end to end checking. I don’t know of a DDR4 equivalent but there might be something in their FAQs.

If you’re feeling particularly suspicious, though, Asus only ever seems to say DDR5 checking and avoids specifically claiming correction support.

Hmm. Thanks for that.

Are you aware of a software way to conclusively test for this? Would a Passmark or OpenSource memtest run attempt to inject errors and see if they are corrected or at least caught?

…or do we just have to live with the uncertainty here?

[lemma]

@mattlach

…or do we just have to live with the uncertainty here?

Confirming SECDED with software or flaky overclocks tends to be pretty tricky. More reliable methods are an interposer or masking a pin.

[Espionage724]

I’ve had a WD Purple 10TB (WD100PURZ) for a few years; reliable and quiet!

[mattlach]

@lemma

Confirming SECDED with software or flaky overclocks tends to be pretty tricky . More reliable methods are an interposer or masking a pin.

Yeah, that is what I had heard.

I don’t really want to mess with inserting masked pins into the socket and risk breaking anything, and I also don’t think it makes sense to spend $275 on an interposer from Passmark that I will use exactly once.

Which results in a bit of a dilemma.

My hope is that the reporting in dmesg is just not properly understanding the dual rank modules, and that everything is actually working properly, but hope is not a strategy…

I may have to try the overclocking method.