Thanks for the heads up!
Just testing with a Test tools server at the moment, seeing if we can install the reg key, will enable it to show up in WSUS as needing to be patched
The superseded the Patches before they could be installed. LOL
Microsoft arenât rushing out the patches without testing⌠Would they
It begins.
Get the Pitchforks
My pitchforks came with a mob!
This is a great read
z87 ?
MaybeâŚ
Well the equifax guys got away with it, so why is anyone suprised?
Mind you, if they had a plan to automatically sell stock, wouldnât this happen frequently? Wouldnât there be a history of it? Or was it a new plan they enacted to automatically sell stock when something bad happens?
Intelâs stock price doesnât seem to have tanked too badly.
The news is mostly nerds only atm. Its on a few news sites. Have to see what happens.
Thanks for the reminder, topic is up next.
Worst day in over two yearsâŚ
iirc the flaw was with the MMU all the way back to P3
Processor
Variant 1
Variant 2
Variant 3
Variant 3a
Cortex-R7
Yes*
Yes*
No
No
Cortex-R8
Yes*
Yes*
No
No
Cortex-A8
Yes (under review)
Yes
No
No
Cortex-A9
Yes
Yes
No
No
Cortex-A15
Yes (under review)
Yes
No
Yes
Cortex-A17
Yes
Yes
No
No
Cortex-A57
Yes
Yes
No
Yes
Cortex-A72
Yes
Yes
No
Yes
Cortex-A73
Yes
Yes
No
No
Cortex-A75
Yes
Yes
Yes
No
-
Note for Cortex-R cores: The common usage model for Cortex-R is in non-open environments where applications or processes are strictly controlled and hence not exploitable.
Step 2If you are running Linux, please follow the directions below according to the variant identified in the table.
If you are running Android, please check with Google for the detail of supported kernel versions.
If you are running another OS, please contact the OS vendor for details.
For JIT development, check the generated code and replace with new instruction sequences as detailed in the Cache Speculation Side-channels whitepaper.
For Linux
Variant 1
Action required:
Search your code for the code snippets as described in the Cache Speculation Side-channels whitepaper. Once identified use the compiler support for mitigations as described in Compiler support for mitigations to modify your code, and recompile using an updated compiler.
Variant 2
The mitigation will vary by processor micro-architecture:
For Cortex-A57 and Cortex-A72:
Apply all kernel patches provided by Arm and available at https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti Also apply all Arm Trusted Firmware patches.
For Cortex-A73:
Apply all kernel patches provided by Arm and available at https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti Also apply all Arm Trusted Firmware patches.
For Cortex-A75:
Apply all kernel patches provided by Arm and available at https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti Also apply all Arm Trusted Firmware patches.
Variant 3
For all affected Arm Cortex-A processors:
Apply all kernel patches provided by Arm and available at https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti There is no need to further check or modify code outside of kernel code.
Variant 3a
In general, it is not believed that software mitigations for this issue are necessary. Please download the Cache Speculation Side-channels whitepaper for more details.
Apple version
As it stands⌠I have yet to find anything definite for Amd or Intel cpus as far a more complete list.